EP2C8 FPGA Development Board SOPC Development Board V5.0
Specific introduction: http://www.yheda.com/Shop/fpga/altera/200809/107.html
The best choice for FPGA development, SOPC development, and Nios development
The V5 series is an upgrade from the V3 series, uniformly upgrading the flash from 2MByte in V3 to 8Mbyte. The V5 experimental board adds two 4-bit digital tubes, 10M network function, A/D conversion, and D/A conversion on the basis of V3, and the learning examples are more abundant.
Note: The kits are all in the form of a core board + experimental board combination
The above prices do not include invoices. An additional 6% tax point is required for invoicing.
We adhere to the concept of practicality all the time, and consider users' needs everywhere. The 5.0 version is carefully crafted on the basis of the 3.0 version. Each function is carefully designed with practical example programs, and detailed tutorials are rewritten. It is very meaningful whether for learning or developing product prototypes. In addition, we design multiple core boards including Cyclone, Cyclone II, etc. for users to choose from, and continuously develop and supply various practical function expansion boards with excellent expansion performance. Whether for learning or development, this kit is a suitable first choice for you.
Quality assurance:
(1) We are committed to providing customers with cost-effective products. Any product is strictly inspected and tested before mailing to ensure that each function works well. If there is a quality problem, it will be replaced free of charge within 7 days, and it is guaranteed for one year. For damage caused by human factors (such as burning the chip due to improper use, etc.), we will still provide free repair, but the chip cost will be charged at cost price.
(2) For customers from other places, we use a well-known air express company for delivery to ensure that the product is delivered to the customer quickly and intactly. If there is damage during delivery, we are responsible for replacement.
(3) We strictly control the quality of the product before leaving the factory, and do three tests on each board before mailing. In case of special circumstances, please contact us in time, and we will give a sincere solution. We regard quality and service as the foundation for customers' long-term trust and cooperation, and also the source of our growth.
Technical support: Methods such as telephone, BBS, QQ, QQ customer groups, etc. are adopted.
The kit includes:
1. FPGA core board: multiple core boards for selection (for information and pictures of each core board, please check the online mall page of this site). The FPGAs used are:
(1) Cyclone core: EP1C12Q240C8, EP1C6Q240C8;
(2) Cyclone II core: EP2C8Q208C8, EP2C5Q208C8, EP2C20Q208C8; Cyclone III core: EP3C16Q240C8, EP3C25Q240C8;
(3) SDRAM: 8MByte;
(4) Flash: 8MByte;
(5) Configuration chip EPCS1 or EPCS4: EP1C6 and EP2C5 core boards are equipped with EPCS1; EP1C12, EP2C8 and EP2C20 core boards are equipped with EPCS4;
(6) Provide configuration modes: JTAG and AS. In addition, the configuration pins are led out through pin headers, which can support the user's future design and use of the PLD + Flash configuration mode;
(7) 50Mhz active clock;
(8) All IO, Avalon bus, configuration pins, etc. are led out through 4-row pin headers, allowing users to give full play and expand more flexibly;
(9) 4 LEDs;
(10) One reset button.
2. The experimental board V5.0 is equipped with:
★10M Ethernet interface: using RTL8019 chip;
★8-bit AD analog-to-digital converter;
★4-channel 8-bit DA digital-to-analog converter;
★Real-time clock;
★RS-232 serial port: used for data communication with the computer;
★VGA interface: directly connect VGA to the display, and use FPGA to implement the VGA interface protocol to display text, graphics, etc. on the display.
★PS/2 mouse and keyboard interface.
★16*2 character LCD interface, which can display English characters.
★128*64 dot matrix LCD interface, which can display Chinese, graphics, etc.;
★Buzzer.
★USB interface:
Adopt USB-UART bridge chip CP2102, compatible with USB1.1 and USB2.0 protocols, with a maximum communication rate of 1Mbps, which can be directly used in occasions where the communication rate is not very high, such as industrial control equipment, instrument meters, etc., which is convenient and practical; developers do not need to understand the USB protocol and design the driver program, just operate the communication like a serial port, thus making the development cycle short, the risk small, and the cost low; in addition, it is small in size, good in anti-interference performance, stable and reliable in work, and the normal working temperature range is: -40 ~ +85°C. In the CD of the kit, the data sheet, driver program, and example program of this chip are attached.
★Two 4-bit 7-segment digital tubes.
★EEPROM memory based on I2C protocol.
★4 button switches: also adhering to the simple style, not pursuing many, but seeking simplicity, saving limited IO resources, which is enough for experiments such as external button input and interrupt of Nios II.
3. ByteBlasterII download cable. If you need to replace it with a USB-Blaster download cable (fully compatible with Altera original USB-Blaster), an additional 120 yuan is required.
4. Other accessories:
(1) 16x2 LCD module, optional, only 20 yuan;
(2) 128x64 dot matrix LCD module, optional, only 80 yuan;
(3) USB2.0 expansion module, optional, 380 yuan;
Special note: All our example source codes are not just the sample codes provided on the Altera website. All example codes are the hard work of our engineers, practical and easy to use. These codes have been carefully debugged by our engineers and tested on each model. These examples are not only for learning, but can also be directly used in actual applications.
5. Supporting list
V5 kit supporting list:
(1) One core board;
(2) One experimental board;
(3) One ByteBlasterII download cable;
(4) One USB cable;
(5) One 5V switching power supply;
(6) One DVD disc containing complete software (QuartusII7.2 and NiosII IDE7.2 version, etc.), experimental manual, document data, etc., as well as detailed circuit schematic (pdf format); provide Protel format component package diagrams of FPGA and other chips.
FPGA experiments:
For FPGA experiments, we provide example projects written in both VHDL and Verilog HDL languages.
The experiments include:
(1) FPGA_LED;
(2) 4-bit 7-segment dynamic scanning digital tube display;
(3) PS2 keyboard interface circuit design;
(4) Buzzer music playing experiment;
(5) LCD display experiment;
(6) UART serial communication experiment;
(7) VGA signal generator experiment;
(8) I2C bus EEPROM reading and writing;
(9) AD conversion data acquisition experiment;
(10) DA digital-to-analog conversion experiment;
SOPC experiments:
The feature of Altera's FPGA lies in the perfection and power of the SOPC system based on the Nios II core. Altera provides a large number of free IP cores for the Nios system and complete API driver functions. This makes our development of the SOPC system more convenient and simple.
The provided SOPC experiments are:
(1) SOPC_LED: the simplest Nios system experiment.
(2) SOPC_LED_BF: Flash burning experiment.
(3) Timer interrupt experiment;
(4) Button interrupt experiment;
(5) DMA transmission experiment;
(6) UART serial communication experiment;
(7) Pulse width modulation PWM experiment;
(8) PS2 keyboard experiment;
(9) Using timer interrupt to generate different frequencies to drive the buzzer to play music experiment;
(10) LCD1602 display experiment, providing HAL API driver functions and standard C library function access.
(11) LCD12864 liquid crystal display experiment, providing complete driver functions and easy to use.
(12) (12) VGA display experiment, using DMA transmission, displaying English, Chinese characters, pictures, animations, etc. with 8 colors and 320*240 resolution on the display.
(13) Real-time clock chip PCF8563 use experiment.
(14) I2C interface EEPROM memory reading and writing experiment.
(15) Network communication experiment: providing a simple_socket_server remote login experiment, and a Web server network server experiment;
(16) AD data acquisition experiment;
(17) DA digital-to-analog conversion experiment;
(18) Custom peripheral digital tube interface design based on the Avalon bus;
(19) Custom instruction experiment;
(20) Floating point instruction use experiment;
(21) Dual Nios II CPU core experiment;
(22) UCOSII operating system experiment;
(23) Uclinux operating system porting experiment (Note: Provide porting tutorials based on QII5.1. QII7.2 needs to be completed under the Linux operating system. This site only provides reference documents);
(24) Provide tutorials and example projects for porting 8051 single-chip microcomputer core to FPGA. Friends who like 8051 can still have fun on FPGA.
The QII7.2 version of the software has been greatly changed compared with the previous version. Many previous tutorial materials are not very applicable to the 7.2 version. To avoid beginners taking too many detours, our documents are rewritten based on the 7.2 version. And for beginners, several detailed experimental tutorials are written to lead beginners to quickly master the application development of FPGA and SOPC step by step.
FPGA_LED: Use one button to control the on/off of one LED. The simplest experiment allows beginners to familiarize themselves with the use of QII software, master the FPGA development process. The document is illustrated with pictures, describing each step and precautions in detail, allowing beginners to easily get started with FPGA development.
FPGA_74SEG: Design a dynamic 4-bit digital tube display circuit and waveform simulation experiment, allowing beginners to gradually enter FPGA development from shallow to deep, and learn and master circuit simulation using QII.
SOPC_LED: Design the simplest SOPC system, composed of Nios II CPU + on-chip memory + LED, learn the basic process of SOPC development, learn the basic use of SOPC Builder and the writing and online debugging of C programs in the Nios integrated development environment (NiosIDE).
SOPC_LED_BF: Add SDRAM controller and Flash controller to the SOPC system, learn the usage methods of SDRAM and Flash, burn the debugged program into Flash, and the program is automatically downloaded to SDRAM for execution after power-on.
EP1C12 type: 880 yuan/set (purchase model: T1C12-V5)
EP2C5 type: 730 yuan/set (purchase model: T2C5-V5)
EP2C8 type: 860 yuan/set (purchase model: T2C8-V5)
EP3C25 type: 1260 yuan/set (purchase model: T3C25-V5)
Freight: 20 yuan
Purchase method: http://www.yheda.com/Article/ShowArticle.asp?ArticleID=8409
QQ: 342665334 952183045
Email: wen_zl@163.com
MSN: wen_zl@163.com
Consultation phone: 13840376790 024-64664047
Website: http://www.yheda.com
Our company also has various DSP development boards, ARM development boards, FPGA development boards, CPLD development boards, single-chip microcomputer development boards and simulators and other development tools. Welcome to consult and purchase! Company website: http://www.yheda.com
DSP products:
2407 development board, 2812 development board, 28335 development board, 5402 development board, 5502 development board, 5509 development board, 6713 development board, 642 development board, XDS510 DSP emulator;
ARM products:
OMAP3530 development board, STM32 development board, NXP/LPC development board, S3C44B0 development board, S3C2410 development board, S3C2440 development board, S3C6410 development board, HJTAG emulator, JLINK emulator, MULTI ICE emulator;
FPGA/CPLD products:
EP1C6 development, EP1C12 development board, EP2C5 development board, EP2C8 development board, EP2C20 development board, EP2C35 development board, EP3C25 development board, XC2S50 development board, XC3S400 development board, XC3S700 development board, XC3S1400 development board, EPM7128 development board, EPM1270 development board, USB BLASTER download cable, XILINX USB download cable, ByteBlasterII download cable;
Single-chip microcomputer products:
51 single-chip microcomputer development board, MSP430 development board, AVR development board, PIC development board, MSP320 emulator, MKII AVR emulator
Specific introduction: http://www.yheda.com/Shop/fpga/altera/200809/107.html
The best choice for FPGA development, SOPC development, and Nios development
The V5 series is an upgrade from the V3 series, uniformly upgrading the flash from 2MByte in V3 to 8Mbyte. The V5 experimental board adds two 4-bit digital tubes, 10M network function, A/D conversion, and D/A conversion on the basis of V3, and the learning examples are more abundant.
Note: The kits are all in the form of a core board + experimental board combination
The above prices do not include invoices. An additional 6% tax point is required for invoicing.
We adhere to the concept of practicality all the time, and consider users' needs everywhere. The 5.0 version is carefully crafted on the basis of the 3.0 version. Each function is carefully designed with practical example programs, and detailed tutorials are rewritten. It is very meaningful whether for learning or developing product prototypes. In addition, we design multiple core boards including Cyclone, Cyclone II, etc. for users to choose from, and continuously develop and supply various practical function expansion boards with excellent expansion performance. Whether for learning or development, this kit is a suitable first choice for you.
Quality assurance:
(1) We are committed to providing customers with cost-effective products. Any product is strictly inspected and tested before mailing to ensure that each function works well. If there is a quality problem, it will be replaced free of charge within 7 days, and it is guaranteed for one year. For damage caused by human factors (such as burning the chip due to improper use, etc.), we will still provide free repair, but the chip cost will be charged at cost price.
(2) For customers from other places, we use a well-known air express company for delivery to ensure that the product is delivered to the customer quickly and intactly. If there is damage during delivery, we are responsible for replacement.
(3) We strictly control the quality of the product before leaving the factory, and do three tests on each board before mailing. In case of special circumstances, please contact us in time, and we will give a sincere solution. We regard quality and service as the foundation for customers' long-term trust and cooperation, and also the source of our growth.
Technical support: Methods such as telephone, BBS, QQ, QQ customer groups, etc. are adopted.
The kit includes:
1. FPGA core board: multiple core boards for selection (for information and pictures of each core board, please check the online mall page of this site). The FPGAs used are:
(1) Cyclone core: EP1C12Q240C8, EP1C6Q240C8;
(2) Cyclone II core: EP2C8Q208C8, EP2C5Q208C8, EP2C20Q208C8; Cyclone III core: EP3C16Q240C8, EP3C25Q240C8;
(3) SDRAM: 8MByte;
(4) Flash: 8MByte;
(5) Configuration chip EPCS1 or EPCS4: EP1C6 and EP2C5 core boards are equipped with EPCS1; EP1C12, EP2C8 and EP2C20 core boards are equipped with EPCS4;
(6) Provide configuration modes: JTAG and AS. In addition, the configuration pins are led out through pin headers, which can support the user's future design and use of the PLD + Flash configuration mode;
(7) 50Mhz active clock;
(8) All IO, Avalon bus, configuration pins, etc. are led out through 4-row pin headers, allowing users to give full play and expand more flexibly;
(9) 4 LEDs;
(10) One reset button.
2. The experimental board V5.0 is equipped with:
★10M Ethernet interface: using RTL8019 chip;
★8-bit AD analog-to-digital converter;
★4-channel 8-bit DA digital-to-analog converter;
★Real-time clock;
★RS-232 serial port: used for data communication with the computer;
★VGA interface: directly connect VGA to the display, and use FPGA to implement the VGA interface protocol to display text, graphics, etc. on the display.
★PS/2 mouse and keyboard interface.
★16*2 character LCD interface, which can display English characters.
★128*64 dot matrix LCD interface, which can display Chinese, graphics, etc.;
★Buzzer.
★USB interface:
Adopt USB-UART bridge chip CP2102, compatible with USB1.1 and USB2.0 protocols, with a maximum communication rate of 1Mbps, which can be directly used in occasions where the communication rate is not very high, such as industrial control equipment, instrument meters, etc., which is convenient and practical; developers do not need to understand the USB protocol and design the driver program, just operate the communication like a serial port, thus making the development cycle short, the risk small, and the cost low; in addition, it is small in size, good in anti-interference performance, stable and reliable in work, and the normal working temperature range is: -40 ~ +85°C. In the CD of the kit, the data sheet, driver program, and example program of this chip are attached.
★Two 4-bit 7-segment digital tubes.
★EEPROM memory based on I2C protocol.
★4 button switches: also adhering to the simple style, not pursuing many, but seeking simplicity, saving limited IO resources, which is enough for experiments such as external button input and interrupt of Nios II.
3. ByteBlasterII download cable. If you need to replace it with a USB-Blaster download cable (fully compatible with Altera original USB-Blaster), an additional 120 yuan is required.
4. Other accessories:
(1) 16x2 LCD module, optional, only 20 yuan;
(2) 128x64 dot matrix LCD module, optional, only 80 yuan;
(3) USB2.0 expansion module, optional, 380 yuan;
Special note: All our example source codes are not just the sample codes provided on the Altera website. All example codes are the hard work of our engineers, practical and easy to use. These codes have been carefully debugged by our engineers and tested on each model. These examples are not only for learning, but can also be directly used in actual applications.
5. Supporting list
V5 kit supporting list:
(1) One core board;
(2) One experimental board;
(3) One ByteBlasterII download cable;
(4) One USB cable;
(5) One 5V switching power supply;
(6) One DVD disc containing complete software (QuartusII7.2 and NiosII IDE7.2 version, etc.), experimental manual, document data, etc., as well as detailed circuit schematic (pdf format); provide Protel format component package diagrams of FPGA and other chips.
FPGA experiments:
For FPGA experiments, we provide example projects written in both VHDL and Verilog HDL languages.
The experiments include:
(1) FPGA_LED;
(2) 4-bit 7-segment dynamic scanning digital tube display;
(3) PS2 keyboard interface circuit design;
(4) Buzzer music playing experiment;
(5) LCD display experiment;
(6) UART serial communication experiment;
(7) VGA signal generator experiment;
(8) I2C bus EEPROM reading and writing;
(9) AD conversion data acquisition experiment;
(10) DA digital-to-analog conversion experiment;
SOPC experiments:
The feature of Altera's FPGA lies in the perfection and power of the SOPC system based on the Nios II core. Altera provides a large number of free IP cores for the Nios system and complete API driver functions. This makes our development of the SOPC system more convenient and simple.
The provided SOPC experiments are:
(1) SOPC_LED: the simplest Nios system experiment.
(2) SOPC_LED_BF: Flash burning experiment.
(3) Timer interrupt experiment;
(4) Button interrupt experiment;
(5) DMA transmission experiment;
(6) UART serial communication experiment;
(7) Pulse width modulation PWM experiment;
(8) PS2 keyboard experiment;
(9) Using timer interrupt to generate different frequencies to drive the buzzer to play music experiment;
(10) LCD1602 display experiment, providing HAL API driver functions and standard C library function access.
(11) LCD12864 liquid crystal display experiment, providing complete driver functions and easy to use.
(12) (12) VGA display experiment, using DMA transmission, displaying English, Chinese characters, pictures, animations, etc. with 8 colors and 320*240 resolution on the display.
(13) Real-time clock chip PCF8563 use experiment.
(14) I2C interface EEPROM memory reading and writing experiment.
(15) Network communication experiment: providing a simple_socket_server remote login experiment, and a Web server network server experiment;
(16) AD data acquisition experiment;
(17) DA digital-to-analog conversion experiment;
(18) Custom peripheral digital tube interface design based on the Avalon bus;
(19) Custom instruction experiment;
(20) Floating point instruction use experiment;
(21) Dual Nios II CPU core experiment;
(22) UCOSII operating system experiment;
(23) Uclinux operating system porting experiment (Note: Provide porting tutorials based on QII5.1. QII7.2 needs to be completed under the Linux operating system. This site only provides reference documents);
(24) Provide tutorials and example projects for porting 8051 single-chip microcomputer core to FPGA. Friends who like 8051 can still have fun on FPGA.
The QII7.2 version of the software has been greatly changed compared with the previous version. Many previous tutorial materials are not very applicable to the 7.2 version. To avoid beginners taking too many detours, our documents are rewritten based on the 7.2 version. And for beginners, several detailed experimental tutorials are written to lead beginners to quickly master the application development of FPGA and SOPC step by step.
FPGA_LED: Use one button to control the on/off of one LED. The simplest experiment allows beginners to familiarize themselves with the use of QII software, master the FPGA development process. The document is illustrated with pictures, describing each step and precautions in detail, allowing beginners to easily get started with FPGA development.
FPGA_74SEG: Design a dynamic 4-bit digital tube display circuit and waveform simulation experiment, allowing beginners to gradually enter FPGA development from shallow to deep, and learn and master circuit simulation using QII.
SOPC_LED: Design the simplest SOPC system, composed of Nios II CPU + on-chip memory + LED, learn the basic process of SOPC development, learn the basic use of SOPC Builder and the writing and online debugging of C programs in the Nios integrated development environment (NiosIDE).
SOPC_LED_BF: Add SDRAM controller and Flash controller to the SOPC system, learn the usage methods of SDRAM and Flash, burn the debugged program into Flash, and the program is automatically downloaded to SDRAM for execution after power-on.
EP1C12 type: 880 yuan/set (purchase model: T1C12-V5)
EP2C5 type: 730 yuan/set (purchase model: T2C5-V5)
EP2C8 type: 860 yuan/set (purchase model: T2C8-V5)
EP3C25 type: 1260 yuan/set (purchase model: T3C25-V5)
Freight: 20 yuan
Purchase method: http://www.yheda.com/Article/ShowArticle.asp?ArticleID=8409
QQ: 342665334 952183045
Email: wen_zl@163.com
MSN: wen_zl@163.com
Consultation phone: 13840376790 024-64664047
Website: http://www.yheda.com
Our company also has various DSP development boards, ARM development boards, FPGA development boards, CPLD development boards, single-chip microcomputer development boards and simulators and other development tools. Welcome to consult and purchase! Company website: http://www.yheda.com
DSP products:
2407 development board, 2812 development board, 28335 development board, 5402 development board, 5502 development board, 5509 development board, 6713 development board, 642 development board, XDS510 DSP emulator;
ARM products:
OMAP3530 development board, STM32 development board, NXP/LPC development board, S3C44B0 development board, S3C2410 development board, S3C2440 development board, S3C6410 development board, HJTAG emulator, JLINK emulator, MULTI ICE emulator;
FPGA/CPLD products:
EP1C6 development, EP1C12 development board, EP2C5 development board, EP2C8 development board, EP2C20 development board, EP2C35 development board, EP3C25 development board, XC2S50 development board, XC3S400 development board, XC3S700 development board, XC3S1400 development board, EPM7128 development board, EPM1270 development board, USB BLASTER download cable, XILINX USB download cable, ByteBlasterII download cable;
Single-chip microcomputer products:
51 single-chip microcomputer development board, MSP430 development board, AVR development board, PIC development board, MSP320 emulator, MKII AVR emulator