3 Collection of hardware and related information of Loongson series computers - China DOS Union Forum

Contents
1 Overview ..................................................................................................................11
1.1 Introduction to Loongson Series Processors ......................................................... 11
1.2 Introduction to Loongson 3A3000/3B3000 ......................................................... 12

2 System Configuration and Control ..........................................................................15
2.1 Chip Working Modes ............................................................................................ 15
2.2 Control Pin Descriptions ...................................................................................... 15
2.3 Cache Coherence .................................................................................................. 17
2.4 Physical Address Space Distribution at the System Node Level ......................... 17
2.5 Address Routing Distribution and Configuration ................................................. 19
2.6 Chip Configuration and Sampling Registers ......................................................... 25

3 GS464e Processor Core ............................................................................................30

4 Shared Cache (SCache) ...........................................................................................32

5 Matrix Processing Accelerator .................................................................................34

6 Inter - processor Core Interrupts and Communications ..........................................37

7 I/O Interrupts ............................................................................................................40

8 Temperature Sensor ..................................................................................................43
8.1 Real - time Temperature Sampling ........................................................................ 43
8.2 High and Low Temperature Interrupt Triggering ................................................. 43
8.3 High Temperature Automatic Frequency Reduction Setting ................................ 44

9 DDR2/3 SDRAM Controller Configuration .............................................................46
9.1 Overview of DDR2/3 SDRAM Controller Functions ............................................. 46
9.2 DDR2/3 SDRAM Read Operation Protocol ......................................................... 46
9.3 DDR2/3 SDRAM Write Operation Protocol ......................................................... 47
9.4 DDR2/3 SDRAM Parameter Configuration Format ............................................. 47

9.5 Software Programming Guide ............................................................................. 51
9.5.1 Initialization Operations ............................................................................ 51
9.5.2 Control of Reset Pins ................................................................................ 51
9.5.3 Leveling .................................................................................................... 53
9.5.3.1 Write Leveling ..............................................................................53
9.5.3.2 Gate Leveling ................................................................................54
9.5.4 Initiating MRS Commands Individually .................................................... 55
9.5.5 Arbitrary Operation Control Bus .............................................................. 56
9.5.6 Self - cycling Test Mode Control .............................................................. 56
9.5.7 ECC Function Usage Control ................................................................... 57

10 HyperTransport Controller ....................................................................................58
10.1 HyperTransport Hardware Setup and Initialization ........................................ 58
10.2 HyperTransport Protocol Support ..................................................................... 61
10.3 HyperTransport Interrupt Support .................................................................... 62
10.4 HyperTransport Address Window ..................................................................... 62
10.4.1 HyperTransport Space ......................................................................... 62
10.4.2 HyperTransport Controller Internal Window Configuration ................. 63

10.5 Configuration Registers ...................................................................................... 64
10.5.1 Bridge Control .................................................................................. 66
10.5.2 Capability Registers ...................................................................... 66
10.5.3 Custom Registers .................................................................................. 69
10.5.4 Receive Diagnostic Registers .................................................................. 71
10.5.5 Interrupt Routing Mode Selection Register .......................................... 71
10.5.6 Receive Buffer Initial Register .............................................................. 71
10.5.7 Receive Address Window Configuration Register ................................ 72
10.5.8 Interrupt Vector Register ....................................................................... 75
10.5.9 Interrupt Enable Register ....................................................................... 78
10.5.10 Interrupt Discovery & Configuration .............................................. 81
10.5.11 POST Address Window Configuration Register ................................... 82
10.5.12 Prefetchable Address Window Configuration Register ....................... 83
10.5.13 UNCACHE Address Window Configuration Register ........................... 84
10.5.14 P2P Address Window Configuration Register .................................... 87
10.5.15 Command Send Buffer Size Register ................................................... 89
10.5.16 Data Send Buffer Size Register ........................................................... 89
10.5.17 Send Buffer Debug Register ................................................................ 89
10.5.18 PHY Impedance Matching Control Register ....................................... 90
10.5.19 Revision ID Register ........................................................................ 91
10.5.20 Error Retry Control Register ............................................................ 91
10.5.21 Retry Count Register ........................................................................ 92
10.5.22 Link Train Register .......................................................................... 92
10.5.23 Training 0 Timeout Short Timer Register ........................................ 93
10.5.24 Training 0 Timeout Long Timer Register ........................................ 94
10.5.25 Training 1 Count Register ............................................................... 94
10.5.26 Training 2 Count Register ............................................................... 94
10.5.27 Training 3 Count Register ............................................................... 94
10.5.28 Software Frequency Configuration Register ..................................... 95
10.5.29 PHY Configuration Register ................................................................ 96
10.5.30 Link Initialization Debug Register ...................................................... 97
10.5.31 LDT Debug Register ............................................................................ 97

10.6 Access Method for HyperTransport Bus Configuration Space ...................... 98
10.7 HyperTransport Multi - processor Support ...................................................... 98

11 Low - Speed IO Controller Configuration ..............................................................101
11.1 PCI Controller .................................................................................................... 101
11.2 LPC Controller .................................................................................................... 106
11.3 UART Controller .................................................................................................. 107
11.3.1 Data Register (DAT) .............................................................................108
11.3.2 Interrupt Enable Register (IER) ........................................................... 108
11.3.3 Interrupt Identification Register (IIR) .................................................. 108
11.3.4 FIFO Control Register (FCR) .............................................................. 109
11.3.5 Line Control Register (LCR) ..................................................................109
11.3.6 MODEM Control Register (MCR) .........................................................111
11.3.7 Line Status Register (LSR) ................................................................... 111
11.3.8 MODEM Status Register (MSR) .........................................................113
11.3.9 Divider Latch ...........................................................................................113
11.4 SPI Controller .................................................................................................... 114
11.4.1 Control Register (SPCR) .......................................................................114
11.4.2 Status Register (SPSR) ....................................................................... 115
11.4.3 Data Register (TxFIFO) .......................................................................115
11.4.4 External Register (SPER) ....................................................................... 115
11.4.5 Parameter Control Register (SFC_PARAM) ........................................ 116
11.4.6 Chip Select Control Register (SFC_SOFTCS) ...................................... 116
11.4.7 Timing Control Register (SFC_TIMING) ............................................. 117

11.5 IO Controller Configuration ............................................................................... 118

12 Chip Configuration Register List ..........................................................................122

13 Hardware and Software Design Guide ...................................................................162
13.1 Hardware Modification Guide ........................................................................... 162
13.2 Frequency Setting Instructions .......................................................................... 163
13.3 PMON Modification Guide .................................................................................. 163
13.4 Kernel Modification Guide ................................................................................. 164

List of Figures
Figure 1 - 1 Loongson 3 System Structure ......................................................................11
Figure 1 - 2 Loongson 3 Node Structure .......................................................................12
Figure 1 - 3 Loongson 3A3000/3B3000 Chip Structure ................................................. 13
Figure 3 - 1 GS464e Structure Diagram ..........................................................................31
Figure 7 - 1 Loongson 3A3000/3B3000 Processor Interrupt Routing Schematic Diagram ............................................. 40
Figure 9 - 1 DDR2 SDRAM Read Operation Protocol .................................................... 47
Figure 9 - 2 DDR2 SDRAM Write Operation Protocol .................................................... 47
Figure 10 - 1 Configuration Access of HT Protocol in Loongson 3A3000/3B3000 ...........................................98
Figure 10 - 2 Interconnection Structure of Four Loongson 3 Nodes .............................99
Figure 10 - 3 8 - bit Interconnection Structure of Two Loongson 3 Nodes .........................100
Figure 10 - 4 16 - bit Interconnection Structure of Two Loongson 3 Nodes ......................100
Figure 11 - 1 Configuration Read/Write Bus Address Generation ...................................105

List of Tables
Table 2 - 1 Control Pin Descriptions ...............................................................................15
Table 2 - 2 System Global Address Distribution at the Node Level ...............................17
Table 2 - 3 Address Distribution within the Node ...........................................................18
Table 2 - 4 Address Distribution within the Node ...........................................................18
Table 2 - 5 Access Attributes of the Space Corresponding to the MMAP Field ............19
Table 2 - 6 First - level Crossbar Address Window Register Table ...................................19
Table 2 - 7 Correspondence between Slave Device Number and the Module at the Second - level XBAR ............................22
Table 2 - 8 Access Attributes of the Space Corresponding to the MMAP Field ............22
Table 2 - 9 Second - level XBAR Address Window Conversion Register Table ............22
Table 2 - 10 Default Address Configuration at the Second - level XBAR .......................25
Table 2 - 11 Chip Configuration Register (Physical Address 0x1fe00180) ......................25
Table 2 - 12 Chip Sampling Register (Physical Address 0x1fe00190) ............................25
Table 2 - 13 Chip Node and Processor Core Software Frequency Multiplication Setting Register (Physical Address 0x1fe001b0) ...27
Table 2 - 14 Chip Memory and HT Clock Software Frequency Multiplication Setting Register (Physical Address 0x1fe001c0) ....28
Table 2 - 15 Chip Processor Core Software Divider Setting Register (Physical Address 0x1fe001d0) ................................28

Table 4 - 1 Shared Cache Lock Window Register Configuration .....................................33
Table 5 - 1 Matrix Processing Programming Interface Description ..............................34
Table 5 - 2 Matrix Processing Register Address Description .........................................35
Table 5 - 3 trans_ctrl Register Description ....................................................................35
Table 5 - 4 trans_status Register Description ................................................................36
Table 6 - 1 Registers Related to Inter - processor Core Interrupts and Their Function Descriptions ......................................37
Table 6 - 2 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 0 ..........................37
Table 6 - 3 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 1 ..........................38
Table 6 - 4 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 2 ..........................38
Table 6 - 5 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 3 ..........................38
Table 7 - 1 Interrupt Control Register ............................................................................41
Table 7 - 2 IO Control Register Address .........................................................................41
Table 7 - 3 Description of Interrupt Routing Registers ...................................................42
Table 7 - 4 Interrupt Routing Register Address ...............................................................42
Table 8 - 1 Temperature Sampling Register Description ..................................................43
Table 8 - 2 High and Low Temperature Interrupt Register Description ..........................44
Table 8 - 3 High Temperature Frequency Reduction Control Register Description ......45

Table 10 - 1 HyperTransport Bus - related Pin Signals ................................................... 58
Table 10 - 2 Commands Receivable at the HyperTransport Receive End ...................... 61
Table 10 - 3 Commands Sent Out in Two Modes ............................................................61
Table 10 - 4 Default Address Window Distribution of 4 HyperTransport Interfaces ..... 62
Table 10 - 5 Address Window Distribution within the Loongson 3 Processor HyperTransport Interface .......................... 63
Table 10 - 6 Address Windows Provided in the HyperTransport Interface of Loongson 3A3000/3B3000 Processor ...........63
Table 10 - 7 List of Software - visible Registers .............................................................64
Table 10 - 8 Bus Reset Control Register Definition ......................................................... 66
Table 10 - 9 Command, Capabilities Pointer, Capability ID Register Definition .............66
Table 10 - 10 Link Config, Link Control Register Definition ......................................... 67
Table 10 - 11 Revision ID, Link Freq, Link Error, Link Freq Cap Register Definition ... 68
Table 10 - 12 Feature Capability Register Definition ..................................................... 69
Table 10 - 13 MISC Register Definition ......................................................................... 69
Table 10 - 14 Receive Diagnostic Register .....................................................................71
Table 10 - 15 Interrupt Routing Mode Selection Register .............................................71
Table 10 - 16 Receive Buffer Initial Register ..................................................................71

Table 10 - 17 HT Bus Receive Address Window 0 Enable (External Access) Register Definition ....................................... 72
Table 10 - 18 HT Bus Receive Address Window 0 Base Address (External Access) Register Definition ............................... 72
Table 10 - 19 HT Bus Receive Address Window 1 Enable (External Access) Register Definition ....................................... 73
Table 10 - 20 HT Bus Receive Address Window 1 Base Address (External Access) Register Definition ............................... 73
Table 10 - 21 HT Bus Receive Address Window 2 Enable (External Access) Register Definition ....................................... 73
Table 10 - 22 HT Bus Receive Address Window 2 Base Address (External Access) Register Definition ............................... 74
Table 10 - 23 HT Bus Receive Address Window 3 Enable (External Access) Register Definition ....................................... 74
Table 10 - 24 HT Bus Receive Address Window 3 Base Address (External Access) Register Definition ............................... 74
Table 10 - 25 HT Bus Receive Address Window 4 Enable (External Access) Register Definition ....................................... 75
Table 10 - 26 HT Bus Receive Address Window 4 Base Address (External Access) Register Definition ............................... 75

Table 10 - 27 HT Bus Interrupt Vector Register Definition (1) ........................................ 76
Table 10 - 28 HT Bus Interrupt Vector Register Definition (2) ........................................ 76
Table 10 - 29 HT Bus Interrupt Vector Register Definition (3) ........................................ 77
Table 10 - 30 HT Bus Interrupt Vector Register Definition (4) ........................................ 77
Table 10 - 31 HT Bus Interrupt Vector Register Definition (6) ........................................ 77
Table 10 - 32 HT Bus Interrupt Vector Register Definition (7) ........................................ 77
Table 10 - 33 HT Bus Interrupt Vector Register Definition (8) ........................................ 78
Table 10 - 34 HT Bus Interrupt Enable Register Definition (1) ........................................ 79
Table 10 - 35 HT Bus Interrupt Enable Register Definition (2) ........................................ 79
Table 10 - 36 HT Bus Interrupt Enable Register Definition (3) ........................................ 79
Table 10 - 37 HT Bus Interrupt Enable Register Definition (4) ........................................ 79
Table 10 - 38 HT Bus Interrupt Enable Register Definition (5) ........................................ 80
Table 10 - 39 HT Bus Interrupt Enable Register Definition (6) ........................................ 80
Table 10 - 40 HT Bus Interrupt Enable Register Definition (7) ........................................ 80
Table 10 - 41 HT Bus Interrupt Enable Register Definition (8) ........................................ 80

Table 10 - 42 Interrupt Capability Register Definition ................................................... 81
Table 10 - 43 Dataport Register Definition .....................................................................81
Table 10 - 44 IntrInfo Register Definition (1) ............................................................... 81
Table 10 - 45 IntrInfo Register Definition (2) ............................................................... 81
Table 10 - 46 HT Bus POST Address Window 0 Enable (Internal Access) .......................82
Table 10 - 47 HT Bus POST Address Window 0 Base Address (Internal Access) ...............82
Table 10 - 48 HT Bus POST Address Window 1 Enable (Internal Access) .......................83
Table 10 - 49 HT Bus POST Address Window 1 Base Address (Internal Access) ...............83
Table 10 - 50 HT Bus Prefetchable Address Window 0 Enable (Internal Access) ............ 83
Table 10 - 51 HT Bus Prefetchable Address Window 0 Base Address (Internal Access) ............ 84
Table 10 - 52 HT Bus Prefetchable Address Window 1 Enable (Internal Access) ............ 84
Table 10 - 53 HT Bus Prefetchable Address Window 1 Base Address (Internal Access) ............ 84
Table 10 - 54 HT Bus Uncache Address Window 0 Enable (Internal Access) ................... 85
Table 10 - 55 HT Bus Uncache Address Window 0 Base Address (Internal Access) ........... 85
Table 10 - 56 HT Bus Uncache Address Window 1 Enable (Internal Access) ................... 85
Table 10 - 57 HT Bus Uncache Address Window 1 Base Address (Internal Access) ........... 86
Table 10 - 58 HT Bus Uncache Address Window 2 Enable (Internal Access) ................... 86
Table 10 - 59 HT Bus Uncache Address Window 2 Base Address (Internal Access) ........... 86
Table 10 - 60 HT Bus Uncache Address Window 3 Enable (Internal Access) ................... 87
Table 10 - 61 HT Bus Uncache Address Window 3 Base Address (Internal Access) ........... 87
Table 10 - 62 HT Bus P2P Address Window 0 Enable (External Access) Register Definition ........................................ 87
Table 10 - 63 HT Bus P2P Address Window 0 Base Address (External Access) Register Definition ........................................ 88
Table 10 - 64 HT Bus P2P Address Window 1 Enable (External Access) Register Definition ........................................ 88
Table 10 - 65 HT Bus P2P Address Window 1 Base Address (External Access) Register Definition ........................................ 88

Table 10 - 66 Command Send Buffer Size Register .........................................................89
Table 10 - 67 Data Send Buffer Size Register .................................................................89
Table 10 - 68 Send Buffer Debug Register .......................................................................90
Table 10 - 69 Impedance Matching Control Register .......................................................91
Table 10 - 70 Revision ID Register ................................................................................. 91
Table 10 - 71 Error Retry Control Register ..................................................................... 91
Table 10 - 72 Retry Count Register ................................................................................. 92
Table 10 - 73 Link Train Register ....................................................................................92
Table 10 - 74 Training 0 Timeout Short Timer Register ................................................. 93
Table 10 - 75 Training 0 Timeout Long Timer Register ................................................. 94
Table 10 - 76 Training 1 Count Register ......................................................................... 94
Table 10 - 77 Training 2 Count Register ......................................................................... 94
Table 10 - 78 Training 3 Count Register ......................................................................... 95
Table 10 - 79 Software Frequency Configuration Register .............................................95
Table 10 - 80 PHY Configuration Register ......................................................................96
Table 10 - 81 Link Initialization Debug Register .............................................................97
Table 10 - 82 LDT Debug Register ................................................................................... 98
Table 11 - 1 PCI Controller Configuration Header .........................................................101
Table 11 - 2 PCI Control Register ...................................................................................102
Table 11 - 3 PCI/PCIX Bus Request and Acknowledge Line Allocation ........................ 105
Table 11 - 4 LPC Controller Address Space Distribution ................................................106
Table 11 - 5 LPC Configuration Register Meaning .......................................................106
Table 11 - 6 SPI Controller Address Space Distribution ................................................. 114
Table 11 - 7 IO Control Register .....................................................................................118
Table 11 - 8 Register Detailed Description .................................................................... 119

[ Last edited by zzz19760225 on 2017-11-21 at 07:57 ]

Floor106　zzz19760225	Posted 2017-10-02 12:48
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Loongson 3A3000/3B3000 Processor User Manual Volume I Multi-core Processor Architecture, Register Description, and System Software Programming Guide V1.3 http://www.loongson.cn/uploadfile/cpu/3A3000/Loongson3A3000_3B3000user1.pdf [ Last edited by zzz19760225 on 2017-11-21 at 08:00 ]

Floor107　zzz19760225	Posted 2017-10-02 12:48
超级版主　Posts 2,020　Credits 3,673
Contents 1 Overview ..................................................................................................................11 1.1 Introduction to Loongson Series Processors ......................................................... 11 1.2 Introduction to Loongson 3A3000/3B3000 ......................................................... 12 2 System Configuration and Control ..........................................................................15 2.1 Chip Working Modes ............................................................................................ 15 2.2 Control Pin Descriptions ...................................................................................... 15 2.3 Cache Coherence .................................................................................................. 17 2.4 Physical Address Space Distribution at the System Node Level ......................... 17 2.5 Address Routing Distribution and Configuration ................................................. 19 2.6 Chip Configuration and Sampling Registers ......................................................... 25 3 GS464e Processor Core ............................................................................................30 4 Shared Cache (SCache) ...........................................................................................32 5 Matrix Processing Accelerator .................................................................................34 6 Inter - processor Core Interrupts and Communications ..........................................37 7 I/O Interrupts ............................................................................................................40 8 Temperature Sensor ..................................................................................................43 8.1 Real - time Temperature Sampling ........................................................................ 43 8.2 High and Low Temperature Interrupt Triggering ................................................. 43 8.3 High Temperature Automatic Frequency Reduction Setting ................................ 44 9 DDR2/3 SDRAM Controller Configuration .............................................................46 9.1 Overview of DDR2/3 SDRAM Controller Functions ............................................. 46 9.2 DDR2/3 SDRAM Read Operation Protocol ......................................................... 46 9.3 DDR2/3 SDRAM Write Operation Protocol ......................................................... 47 9.4 DDR2/3 SDRAM Parameter Configuration Format ............................................. 47 9.5 Software Programming Guide ............................................................................. 51 9.5.1 Initialization Operations ............................................................................ 51 9.5.2 Control of Reset Pins ................................................................................ 51 9.5.3 Leveling .................................................................................................... 53 9.5.3.1 Write Leveling ..............................................................................53 9.5.3.2 Gate Leveling ................................................................................54 9.5.4 Initiating MRS Commands Individually .................................................... 55 9.5.5 Arbitrary Operation Control Bus .............................................................. 56 9.5.6 Self - cycling Test Mode Control .............................................................. 56 9.5.7 ECC Function Usage Control ................................................................... 57 10 HyperTransport Controller ....................................................................................58 10.1 HyperTransport Hardware Setup and Initialization ........................................ 58 10.2 HyperTransport Protocol Support ..................................................................... 61 10.3 HyperTransport Interrupt Support .................................................................... 62 10.4 HyperTransport Address Window ..................................................................... 62 10.4.1 HyperTransport Space ......................................................................... 62 10.4.2 HyperTransport Controller Internal Window Configuration ................. 63 10.5 Configuration Registers ...................................................................................... 64 10.5.1 Bridge Control .................................................................................. 66 10.5.2 Capability Registers ...................................................................... 66 10.5.3 Custom Registers .................................................................................. 69 10.5.4 Receive Diagnostic Registers .................................................................. 71 10.5.5 Interrupt Routing Mode Selection Register .......................................... 71 10.5.6 Receive Buffer Initial Register .............................................................. 71 10.5.7 Receive Address Window Configuration Register ................................ 72 10.5.8 Interrupt Vector Register ....................................................................... 75 10.5.9 Interrupt Enable Register ....................................................................... 78 10.5.10 Interrupt Discovery & Configuration .............................................. 81 10.5.11 POST Address Window Configuration Register ................................... 82 10.5.12 Prefetchable Address Window Configuration Register ....................... 83 10.5.13 UNCACHE Address Window Configuration Register ........................... 84 10.5.14 P2P Address Window Configuration Register .................................... 87 10.5.15 Command Send Buffer Size Register ................................................... 89 10.5.16 Data Send Buffer Size Register ........................................................... 89 10.5.17 Send Buffer Debug Register ................................................................ 89 10.5.18 PHY Impedance Matching Control Register ....................................... 90 10.5.19 Revision ID Register ........................................................................ 91 10.5.20 Error Retry Control Register ............................................................ 91 10.5.21 Retry Count Register ........................................................................ 92 10.5.22 Link Train Register .......................................................................... 92 10.5.23 Training 0 Timeout Short Timer Register ........................................ 93 10.5.24 Training 0 Timeout Long Timer Register ........................................ 94 10.5.25 Training 1 Count Register ............................................................... 94 10.5.26 Training 2 Count Register ............................................................... 94 10.5.27 Training 3 Count Register ............................................................... 94 10.5.28 Software Frequency Configuration Register ..................................... 95 10.5.29 PHY Configuration Register ................................................................ 96 10.5.30 Link Initialization Debug Register ...................................................... 97 10.5.31 LDT Debug Register ............................................................................ 97 10.6 Access Method for HyperTransport Bus Configuration Space ...................... 98 10.7 HyperTransport Multi - processor Support ...................................................... 98 11 Low - Speed IO Controller Configuration ..............................................................101 11.1 PCI Controller .................................................................................................... 101 11.2 LPC Controller .................................................................................................... 106 11.3 UART Controller .................................................................................................. 107 11.3.1 Data Register (DAT) .............................................................................108 11.3.2 Interrupt Enable Register (IER) ........................................................... 108 11.3.3 Interrupt Identification Register (IIR) .................................................. 108 11.3.4 FIFO Control Register (FCR) .............................................................. 109 11.3.5 Line Control Register (LCR) ..................................................................109 11.3.6 MODEM Control Register (MCR) .........................................................111 11.3.7 Line Status Register (LSR) ................................................................... 111 11.3.8 MODEM Status Register (MSR) .........................................................113 11.3.9 Divider Latch ...........................................................................................113 11.4 SPI Controller .................................................................................................... 114 11.4.1 Control Register (SPCR) .......................................................................114 11.4.2 Status Register (SPSR) ....................................................................... 115 11.4.3 Data Register (TxFIFO) .......................................................................115 11.4.4 External Register (SPER) ....................................................................... 115 11.4.5 Parameter Control Register (SFC_PARAM) ........................................ 116 11.4.6 Chip Select Control Register (SFC_SOFTCS) ...................................... 116 11.4.7 Timing Control Register (SFC_TIMING) ............................................. 117 11.5 IO Controller Configuration ............................................................................... 118 12 Chip Configuration Register List ..........................................................................122 13 Hardware and Software Design Guide ...................................................................162 13.1 Hardware Modification Guide ........................................................................... 162 13.2 Frequency Setting Instructions .......................................................................... 163 13.3 PMON Modification Guide .................................................................................. 163 13.4 Kernel Modification Guide ................................................................................. 164 List of Figures Figure 1 - 1 Loongson 3 System Structure ......................................................................11 Figure 1 - 2 Loongson 3 Node Structure .......................................................................12 Figure 1 - 3 Loongson 3A3000/3B3000 Chip Structure ................................................. 13 Figure 3 - 1 GS464e Structure Diagram ..........................................................................31 Figure 7 - 1 Loongson 3A3000/3B3000 Processor Interrupt Routing Schematic Diagram ............................................. 40 Figure 9 - 1 DDR2 SDRAM Read Operation Protocol .................................................... 47 Figure 9 - 2 DDR2 SDRAM Write Operation Protocol .................................................... 47 Figure 10 - 1 Configuration Access of HT Protocol in Loongson 3A3000/3B3000 ...........................................98 Figure 10 - 2 Interconnection Structure of Four Loongson 3 Nodes .............................99 Figure 10 - 3 8 - bit Interconnection Structure of Two Loongson 3 Nodes .........................100 Figure 10 - 4 16 - bit Interconnection Structure of Two Loongson 3 Nodes ......................100 Figure 11 - 1 Configuration Read/Write Bus Address Generation ...................................105 List of Tables Table 2 - 1 Control Pin Descriptions ...............................................................................15 Table 2 - 2 System Global Address Distribution at the Node Level ...............................17 Table 2 - 3 Address Distribution within the Node ...........................................................18 Table 2 - 4 Address Distribution within the Node ...........................................................18 Table 2 - 5 Access Attributes of the Space Corresponding to the MMAP Field ............19 Table 2 - 6 First - level Crossbar Address Window Register Table ...................................19 Table 2 - 7 Correspondence between Slave Device Number and the Module at the Second - level XBAR ............................22 Table 2 - 8 Access Attributes of the Space Corresponding to the MMAP Field ............22 Table 2 - 9 Second - level XBAR Address Window Conversion Register Table ............22 Table 2 - 10 Default Address Configuration at the Second - level XBAR .......................25 Table 2 - 11 Chip Configuration Register (Physical Address 0x1fe00180) ......................25 Table 2 - 12 Chip Sampling Register (Physical Address 0x1fe00190) ............................25 Table 2 - 13 Chip Node and Processor Core Software Frequency Multiplication Setting Register (Physical Address 0x1fe001b0) ...27 Table 2 - 14 Chip Memory and HT Clock Software Frequency Multiplication Setting Register (Physical Address 0x1fe001c0) ....28 Table 2 - 15 Chip Processor Core Software Divider Setting Register (Physical Address 0x1fe001d0) ................................28 Table 4 - 1 Shared Cache Lock Window Register Configuration .....................................33 Table 5 - 1 Matrix Processing Programming Interface Description ..............................34 Table 5 - 2 Matrix Processing Register Address Description .........................................35 Table 5 - 3 trans_ctrl Register Description ....................................................................35 Table 5 - 4 trans_status Register Description ................................................................36 Table 6 - 1 Registers Related to Inter - processor Core Interrupts and Their Function Descriptions ......................................37 Table 6 - 2 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 0 ..........................37 Table 6 - 3 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 1 ..........................38 Table 6 - 4 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 2 ..........................38 Table 6 - 5 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 3 ..........................38 Table 7 - 1 Interrupt Control Register ............................................................................41 Table 7 - 2 IO Control Register Address .........................................................................41 Table 7 - 3 Description of Interrupt Routing Registers ...................................................42 Table 7 - 4 Interrupt Routing Register Address ...............................................................42 Table 8 - 1 Temperature Sampling Register Description ..................................................43 Table 8 - 2 High and Low Temperature Interrupt Register Description ..........................44 Table 8 - 3 High Temperature Frequency Reduction Control Register Description ......45 Table 10 - 1 HyperTransport Bus - related Pin Signals ................................................... 58 Table 10 - 2 Commands Receivable at the HyperTransport Receive End ...................... 61 Table 10 - 3 Commands Sent Out in Two Modes ............................................................61 Table 10 - 4 Default Address Window Distribution of 4 HyperTransport Interfaces ..... 62 Table 10 - 5 Address Window Distribution within the Loongson 3 Processor HyperTransport Interface .......................... 63 Table 10 - 6 Address Windows Provided in the HyperTransport Interface of Loongson 3A3000/3B3000 Processor ...........63 Table 10 - 7 List of Software - visible Registers .............................................................64 Table 10 - 8 Bus Reset Control Register Definition ......................................................... 66 Table 10 - 9 Command, Capabilities Pointer, Capability ID Register Definition .............66 Table 10 - 10 Link Config, Link Control Register Definition ......................................... 67 Table 10 - 11 Revision ID, Link Freq, Link Error, Link Freq Cap Register Definition ... 68 Table 10 - 12 Feature Capability Register Definition ..................................................... 69 Table 10 - 13 MISC Register Definition ......................................................................... 69 Table 10 - 14 Receive Diagnostic Register .....................................................................71 Table 10 - 15 Interrupt Routing Mode Selection Register .............................................71 Table 10 - 16 Receive Buffer Initial Register ..................................................................71 Table 10 - 17 HT Bus Receive Address Window 0 Enable (External Access) Register Definition ....................................... 72 Table 10 - 18 HT Bus Receive Address Window 0 Base Address (External Access) Register Definition ............................... 72 Table 10 - 19 HT Bus Receive Address Window 1 Enable (External Access) Register Definition ....................................... 73 Table 10 - 20 HT Bus Receive Address Window 1 Base Address (External Access) Register Definition ............................... 73 Table 10 - 21 HT Bus Receive Address Window 2 Enable (External Access) Register Definition ....................................... 73 Table 10 - 22 HT Bus Receive Address Window 2 Base Address (External Access) Register Definition ............................... 74 Table 10 - 23 HT Bus Receive Address Window 3 Enable (External Access) Register Definition ....................................... 74 Table 10 - 24 HT Bus Receive Address Window 3 Base Address (External Access) Register Definition ............................... 74 Table 10 - 25 HT Bus Receive Address Window 4 Enable (External Access) Register Definition ....................................... 75 Table 10 - 26 HT Bus Receive Address Window 4 Base Address (External Access) Register Definition ............................... 75 Table 10 - 27 HT Bus Interrupt Vector Register Definition (1) ........................................ 76 Table 10 - 28 HT Bus Interrupt Vector Register Definition (2) ........................................ 76 Table 10 - 29 HT Bus Interrupt Vector Register Definition (3) ........................................ 77 Table 10 - 30 HT Bus Interrupt Vector Register Definition (4) ........................................ 77 Table 10 - 31 HT Bus Interrupt Vector Register Definition (6) ........................................ 77 Table 10 - 32 HT Bus Interrupt Vector Register Definition (7) ........................................ 77 Table 10 - 33 HT Bus Interrupt Vector Register Definition (8) ........................................ 78 Table 10 - 34 HT Bus Interrupt Enable Register Definition (1) ........................................ 79 Table 10 - 35 HT Bus Interrupt Enable Register Definition (2) ........................................ 79 Table 10 - 36 HT Bus Interrupt Enable Register Definition (3) ........................................ 79 Table 10 - 37 HT Bus Interrupt Enable Register Definition (4) ........................................ 79 Table 10 - 38 HT Bus Interrupt Enable Register Definition (5) ........................................ 80 Table 10 - 39 HT Bus Interrupt Enable Register Definition (6) ........................................ 80 Table 10 - 40 HT Bus Interrupt Enable Register Definition (7) ........................................ 80 Table 10 - 41 HT Bus Interrupt Enable Register Definition (8) ........................................ 80 Table 10 - 42 Interrupt Capability Register Definition ................................................... 81 Table 10 - 43 Dataport Register Definition .....................................................................81 Table 10 - 44 IntrInfo Register Definition (1) ............................................................... 81 Table 10 - 45 IntrInfo Register Definition (2) ............................................................... 81 Table 10 - 46 HT Bus POST Address Window 0 Enable (Internal Access) .......................82 Table 10 - 47 HT Bus POST Address Window 0 Base Address (Internal Access) ...............82 Table 10 - 48 HT Bus POST Address Window 1 Enable (Internal Access) .......................83 Table 10 - 49 HT Bus POST Address Window 1 Base Address (Internal Access) ...............83 Table 10 - 50 HT Bus Prefetchable Address Window 0 Enable (Internal Access) ............ 83 Table 10 - 51 HT Bus Prefetchable Address Window 0 Base Address (Internal Access) ............ 84 Table 10 - 52 HT Bus Prefetchable Address Window 1 Enable (Internal Access) ............ 84 Table 10 - 53 HT Bus Prefetchable Address Window 1 Base Address (Internal Access) ............ 84 Table 10 - 54 HT Bus Uncache Address Window 0 Enable (Internal Access) ................... 85 Table 10 - 55 HT Bus Uncache Address Window 0 Base Address (Internal Access) ........... 85 Table 10 - 56 HT Bus Uncache Address Window 1 Enable (Internal Access) ................... 85 Table 10 - 57 HT Bus Uncache Address Window 1 Base Address (Internal Access) ........... 86 Table 10 - 58 HT Bus Uncache Address Window 2 Enable (Internal Access) ................... 86 Table 10 - 59 HT Bus Uncache Address Window 2 Base Address (Internal Access) ........... 86 Table 10 - 60 HT Bus Uncache Address Window 3 Enable (Internal Access) ................... 87 Table 10 - 61 HT Bus Uncache Address Window 3 Base Address (Internal Access) ........... 87 Table 10 - 62 HT Bus P2P Address Window 0 Enable (External Access) Register Definition ........................................ 87 Table 10 - 63 HT Bus P2P Address Window 0 Base Address (External Access) Register Definition ........................................ 88 Table 10 - 64 HT Bus P2P Address Window 1 Enable (External Access) Register Definition ........................................ 88 Table 10 - 65 HT Bus P2P Address Window 1 Base Address (External Access) Register Definition ........................................ 88 Table 10 - 66 Command Send Buffer Size Register .........................................................89 Table 10 - 67 Data Send Buffer Size Register .................................................................89 Table 10 - 68 Send Buffer Debug Register .......................................................................90 Table 10 - 69 Impedance Matching Control Register .......................................................91 Table 10 - 70 Revision ID Register ................................................................................. 91 Table 10 - 71 Error Retry Control Register ..................................................................... 91 Table 10 - 72 Retry Count Register ................................................................................. 92 Table 10 - 73 Link Train Register ....................................................................................92 Table 10 - 74 Training 0 Timeout Short Timer Register ................................................. 93 Table 10 - 75 Training 0 Timeout Long Timer Register ................................................. 94 Table 10 - 76 Training 1 Count Register ......................................................................... 94 Table 10 - 77 Training 2 Count Register ......................................................................... 94 Table 10 - 78 Training 3 Count Register ......................................................................... 95 Table 10 - 79 Software Frequency Configuration Register .............................................95 Table 10 - 80 PHY Configuration Register ......................................................................96 Table 10 - 81 Link Initialization Debug Register .............................................................97 Table 10 - 82 LDT Debug Register ................................................................................... 98 Table 11 - 1 PCI Controller Configuration Header .........................................................101 Table 11 - 2 PCI Control Register ...................................................................................102 Table 11 - 3 PCI/PCIX Bus Request and Acknowledge Line Allocation ........................ 105 Table 11 - 4 LPC Controller Address Space Distribution ................................................106 Table 11 - 5 LPC Configuration Register Meaning .......................................................106 Table 11 - 6 SPI Controller Address Space Distribution ................................................. 114 Table 11 - 7 IO Control Register .....................................................................................118 Table 11 - 8 Register Detailed Description .................................................................... 119 [ Last edited by zzz19760225 on 2017-11-21 at 07:57 ]

Floor108　zzz19760225	Posted 2017-10-02 12:48
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Overview, classification introduction, diagrams, lists. 3 GS464e processor core.....................................................................................................30 12 Chip configuration register list..........................................................................................122 13 Hardware and software design guide..................................................................................................162 13.1 Hardware modification guide............................................................................................. 162 [ Last edited by zzz19760225 on 2017-11-21 at 08:01 ]

Floor117　zzz19760225	Posted 2017-10-02 12:48
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Longxin 1A has the following key features: • Integrates one LS232 dual-issue Longxin processor core, with 16KB each for instruction and data L1 Cache • Integrates 2D GPU • Integrates two-way DC controllers, with maximum resolution supporting up to 19201080@60Hz/24bit • Integrates 2 10M/100M/1000M adaptive GMACs • Integrates 2 SATA2s • Integrates 32-bit PCI, supporting master-slave mode • Integrates a 32-bit/16-bit DDR2 controller • Integrates 4 USB HOST interfaces, compatible with USB2.0 and USB1.1 • Integrates an 8-bit NAND FLASH controller, supporting 4 chip selects • Integrates an interrupt controller, supporting flexible interrupt settings • Integrates 2 SPI controllers, supporting master mode, SPI0 supporting system boot • Integrates AC97 controller • Integrates a LPC controller • Integrates 4 UART serial ports • Integrates 1 PS/2 (keyboard and mouse) • Integrates 3 I2C controllers, compatible with SMBUS • Integrates 2 CAN bus controllers • Integrates 88 GPIO ports • Integrates 1 RTC interface • Integrates 4 PWM controllers • Integrates ACPI • Integrates watchdog [ Last edited by zzz19760225 on 2017-12-25 at 13:51* ]

Floor119　zzz19760225	Posted 2017-10-02 12:49
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zhengruohuang: Toddler C Language Operating System https://github.com/zhengruohuang/toddler How to write a simple operating system from scratch? https://www.zhihu.com/question/25628124 [ Last edited by zzz19760225 on 2017-12-7 at 15:21 ]

Floor109　zzz19760225	Posted 2017-10-02 12:48
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Floor118　zzz19760225	Posted 2017-10-02 12:48
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Floor120　zzz19760225	Posted 2017-10-02 12:49
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Loongson2F_Loongson Linglong 9S2A all-in-one machine attempts USB and hard disk installation of Debian 6 success story: linkasm http://blog.csdn.net/v80/article/details/78595967 [ Last edited by zzz19760225 on 2017-11-23 at 15:30 ]