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[ Last edited by zzz19760225 on 2018-9-19 at 19:12 ]

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What is packaging?

What is packaging?
Common Sense of IC Product Packaging
1. What is packaging
Packaging refers to connecting the circuit pins on the silicon chip to the external connectors to facilitate connection with other devices. The packaging form refers to the housing for installing semiconductor integrated circuit chips. It not only plays roles such as installation, fixation, sealing, protection of the chip, and enhancement of thermal and electrical performance, but also connects the pads on the chip to the pins of the packaging housing through wires. These pins are then connected to other devices through the wires on the printed circuit board, thereby achieving the connection between the internal chip and the external circuit. Because the chip must be isolated from the outside world to prevent the corrosion of the chip circuit by impurities in the air from degrading the electrical performance. On the other hand, the packaged chip is also more convenient for installation and transportation. Since the quality of the packaging technology directly affects the performance of the chip itself and the design and manufacturing of the PCB (printed circuit board) connected to it, it is crucial.
The important indicator to measure the advancedness of a chip packaging technology is the ratio of the chip area to the packaging area. The closer this ratio is to 1, the better. The main factors considered during packaging:
1. The ratio of the chip area to the packaging area is as close to 1:1 as possible to improve packaging efficiency;
2. The pins should be as short as possible to reduce delay, and the distance between the pins should be as far as possible to ensure no interference with each other and improve performance;
3. For heat dissipation requirements, the packaging should be as thin as possible.
Packaging is mainly divided into two types: DIP dual in-line and SMD surface mount packaging. In terms of structure, packaging has developed from the earliest transistor TO (such as TO-89, TO92) packaging to dual in-line packaging, then the SOP small outline package was developed by PHILIP, and then gradually derived SOJ (J-leaded small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (shrink small outline package), TSSOP (thin shrink small outline package), and SOT (small outline transistor), SOIC (small outline integrated circuit), etc. In terms of material media, including metal, ceramic, plastic, plastic. Currently, many circuits with high-strength working condition requirements such as military and aerospace levels still have a large number of metal packages.
Packaging has roughly gone through the following development processes:
Structure: TO -> DIP -> PLCC -> QFP -> BGA -> CSP;
Material: metal, ceramic -> ceramic, plastic -> plastic;
Pin shape: long lead through-hole -> short lead or leadless surface mount -> ball bump;
Assembly method: through-hole insertion -> surface mount -> direct installation
2. Specific packaging forms
1. SOP/SOIC packaging
SOP is the abbreviation of Small Outline Package, that is, small outline package. The SOP packaging technology was successfully developed by Philips in 1968-1969, and then gradually derived SOJ (J-leaded small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (shrink small outline package), TSSOP (thin shrink small outline package), and SOT (small outline transistor), SOIC (small outline integrated circuit), etc.
2. DIP packaging
DIP is the abbreviation of Double In-line Package, that is, dual in-line package. One of the through-hole mounting packages, the pins are led out from both sides of the package, and the packaging materials are plastic and ceramic. DIP is the most popular through-hole mounting package, and its application ranges include standard logic ICs, memory LSIs, microcomputer circuits, etc.
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3. PLCC packaging
PLCC is the abbreviation of Plastic Leaded Chip Carrier, that is, plastic J-leaded chip carrier. In the PLCC packaging method, the shape is square, with 32 pins, and there are pins on all four sides. The external dimensions are much smaller than the DIP packaging. The PLCC packaging is suitable for mounting and wiring on the PCB using SMT surface mount technology, and has the advantages of small external dimensions and high reliability.
4. TQFP packaging
TQFP is the abbreviation of thin quad flat package, that is, thin plastic quad flat package. The quad flat package (TQFP) process can effectively use space, thereby reducing the requirements for the space size of the printed circuit board. Because the height and volume are reduced, this packaging process is very suitable for applications with high space requirements, such as PCMCIA cards and network devices. Almost all ALTERA's CPLD/FPGA have TQFP packaging.
5. PQFP packaging
PQFP is the abbreviation of Plastic Quad Flat Package, that is, plastic quad flat package. The chip pins of the PQFP packaging are very close to each other, and the pins are very thin. Generally, large-scale or very large-scale integrated circuits use this packaging form, and the number of its pins is generally more than 100.
6. TSOP packaging
TSOP is the abbreviation of Thin Small Outline Package, that is, thin small size package. A typical feature of the TSOP memory packaging technology is that pins are made around the packaged chip. TSOP is suitable for mounting and wiring on the PCB (printed circuit board) using SMT technology (surface mount technology). When the TSOP packaging has an external dimension, the parasitic parameters (when the current changes drastically, causing output voltage disturbances) are reduced, suitable for high-frequency applications, easy to operate, and relatively high reliability.
7. BGA packaging
BGA is the abbreviation of Ball Grid Array Package, that is, ball grid array package. With the progress of technology in the 1990s, the chip integration degree has continuously increased, the number of I/O pins has increased sharply, and the power consumption has also increased, so the requirements for integrated circuit packaging have become more stringent. In order to meet the development needs, BGA packaging began to be applied in production.
The memory packaged using BGA technology can increase the memory capacity by two to three times without changing the volume of the memory. Compared with TSOP, BGA has a smaller volume, better heat dissipation performance and electrical performance. The BGA packaging technology has greatly increased the storage capacity per square inch. The memory product using BGA packaging technology has a volume only one-third of that of TSOP packaging under the same capacity; in addition, compared with the traditional TSOP packaging method, the BGA packaging method has a more rapid and effective heat dissipation path.
The I/O terminals of BGA packaging are distributed in an array form in the form of circular or columnar solder joints under the package. The advantage of BGA technology is that although the number of I/O pins has increased, the pin pitch has not decreased but increased, thereby improving the assembly yield; although its power consumption has increased, BGA can use the controlled collapse chip method for soldering, thereby improving its thermal and electrical performance; both the thickness and weight are reduced compared with previous packaging technologies; the parasitic parameters are reduced, the signal transmission delay is small, and the use frequency is greatly improved; the assembly can use coplanar soldering, and the reliability is high.
When it comes to BGA packaging, we cannot fail to mention Kingmax's patented TinyBGA technology. TinyBGA is the full name of Tiny Ball Grid Array (small ball grid array package), which is a branch of BGA packaging technology. It was successfully developed by Kingmax in August 1998. The ratio of the chip area to the packaging area is not less than 1:1.14, which can increase the memory capacity by 2-3 times without changing the volume of the memory. Compared with TSOP packaged products, it has a smaller volume, better heat dissipation performance and electrical performance.
The memory product using TinyBGA packaging technology has a volume only 1/3 of that of TSOP packaging under the same capacity. The pins of TSOP packaged memory are led out from the four sides of the chip, while TinyBGA is led out from the center direction of the chip.
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This method effectively shortens the signal conduction distance. The length of the signal transmission line is only 1/4 of the traditional TSOP technology, so the signal attenuation is also reduced. This not only greatly improves the anti-interference and anti-noise performance of the chip, but also improves the electrical performance. The chip packaged with TinyBGA can resist an external frequency of up to 300MHz, while the traditional TSOP packaging technology can only resist an external frequency of up to 150MHz.
The memory packaged with TinyBGA is also thinner in thickness (the packaging height is less than 0.8mm), and the effective heat dissipation path from the metal substrate to the heat sink is only 0.36mm. Therefore, TinyBGA memory has a higher thermal conduction efficiency, which is very suitable for systems that run for a long time and has excellent stability.
3. Naming rules data for packaging of international part brand products
1. MAXIM For more information, please refer to www.maxim-ic.com
The MAXIM prefix is "MAX". DALLAS starts with "DS".
MAX××× or MAX××××
Explanation:
1. Suffixes CSA, CWA, where C represents the general grade, S represents surface mount, and W represents wide body surface mount.
2. Suffix CWI represents wide body surface mount, EEWI represents wide body industrial grade surface mount, suffixes MJA or 883 represent military grade.
3. Suffixes CPA, BCPI, BCPP, CPP, CCPP, CPE, CPD, ACPA all represent general dual in-line.
Example MAX202CPE, CPE general ECPE general with anti-static protection
MAX202EEPE industrial grade anti-static protection (-45°C-85°C), indicating that E represents anti-static protection MAXIM digital arrangement classification
1 series simulator 2 series filter 3 series multiplex switch
4 series amplifier 5 series digital-to-analog converter 6 series voltage reference
7 series voltage conversion 8 series reset device 9 series comparator
DALLAS naming rules
For example DS1210N.S. DS1225Y-100IND
N = industrial grade S = surface mount wide body MCG = DIP package Z = surface mount wide body MNG = DIP industrial grade
IND = industrial grade QCG = PLCC package Q = QFP
2. ADI For more information, please view www.analog.com
AD products are mostly "AD", "ADV", and there are also those starting with "OP" or "REF", "AMP", "SMP", "SSM", "TMP", "TMS", etc.
Explanation of suffixes:
1. Suffix J represents civilian products (0-70°C), N represents general plastic package, and suffix with R represents surface mount.
2. Suffix with D or Q represents ceramic package, industrial grade (45°C-85°C). Suffix with H represents round cap.
3. Suffix SD or 883 belongs to military grade.
For example: JN DIP package JR surface mount JD DIP ceramic
3. BB For more information, please view www.ti.com
BB product naming rules:
Prefix ADS analog device Suffix U surface mount P is DIP package With B represents industrial grade Prefix INA, XTR, PGA, etc. represent high-precision operational amplifiers Suffix U surface mount P represents DIP PA represents high precision
4. INTEL For more information, please view www.intel.com
INTEL product naming rules:
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N80C196 series are all microcontrollers
Prefix: N = PLCC package T = industrial grade S = TQFP package P = DIP package
KC20 main frequency KB main frequency MC represents 84 pins
Example: TE28F640J3A-120 flash memory TE = TSOP DA = SSOP E = TSOP
5. ISSI For more information, please view www.issi.com
Start with "IS"
For example: IS61C IS61LV 4× represents DRAM 6× represents SRAM 9× represents EEPROM
Packaging: PL = PLCC PQ = PQFP T = TSOP TQ = TQFP
6. LINEAR For more information, please view www.linear-tech.com
Prefix with product name
LTC1051CS CS represents surface mount
LTC1051CN8 ** represents *IP package with 8 pins
7. IDT For more information, please view www.idt.com
IDT's products generally start with IDT
Explanation of suffixes:
1. Suffix TP belongs to narrow body DIP
2. Suffix P belongs to wide body DIP
3. Suffix J belongs to PLCC
For example: IDT7134SA55P is DIP package
IDT7132SA55J is PLCC
IDT7206L25TP is DIP
8. NS For more information, please view www.national.com
Some of NS's products start with LM, LF
LM324N 3 series represents civilian products with N round cap
LM224N 2 series represents industrial grade with J ceramic package
LM124J 1 series represents military grade with N plastic package
9. HYNIX For more information, please view www.hynix.com
Packaging: DP represents DIP package DG represents SOP package DT represents TSOP package. Any deficiencies are welcome to be supplemented

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1. BGA (ball grid array)
Ball contact array, one of the surface mount packaging types. The spherical bumps are made on the back of the printed circuit board in an array form instead of pins. The LSI chip is assembled on the front of the printed circuit board, and then sealed with a molded resin or potting method. It is also called bump array carrier (PAC). The number of pins can exceed 200, which is a package for multi-pin LSI. The package body can also be made smaller than QFP (quad flat package). For example, a 360-pin BGA with a pin center distance of 1.5mm is only 31mm square; while a 304-pin QFP with a pin center distance of 0.5mm is 40mm square. Moreover, BGA does not have to worry about the pin deformation problem like QFP. This package was developed by Motorola in the United States and was first used in devices such as mobile phones. It may be popularized in personal computers in the United States in the future. Initially, the pin (bump) center distance of BGA was 1.5mm, and the number of pins was 225. Now some LSI manufacturers are also developing 500-pin BGA. The problem with BGA is the appearance inspection after reflow soldering. It is not yet clear whether an effective appearance inspection method is available. Some people think that since the center distance of the soldering is relatively large, the connection can be regarded as stable, and it can only be handled through functional inspection. Motorola in the United States calls the package sealed with molded resin OMPAC, and the package sealed with potting method GPAC (see OMPAC and GPAC).
2. BQFP (quad flat package with bumper)
Quad flat package with bumper. One of the QFP packages. Protrusions (bumper pads) are provided at the four corners of the package body to prevent the pins from bending and deforming during transportation. American semiconductor manufacturers mainly use this package in microprocessors and ASICs and other circuits. The pin center distance is 0.635mm, and the number of pins is about 84 to 196 (see QFP).
3. Butt joint pin grid array (butt joint pin grid array)
Another name for surface mount type PGA (see surface mount type PGA).
4. C- (ceramic)
Mark indicating ceramic package. For example, CDIP represents ceramic DIP. It is a frequently used mark in practice.
5. Cerdip
Glass-sealed ceramic dual in-line package, used in ECL RAM, DSP (digital signal processor) and other circuits. Cerdip with a glass window is used in UV erasable EPROM and microcomputer circuits with internal EPROM, etc. The pin center distance is 2.54mm, and the number of pins is from 8 to 42. In Japan, this package is represented as DIP-G (G means glass-sealed).
6. Cerquad
One of the surface mount packaging types, that is, ceramic QFP sealed below, used for packaging logic LSI circuits such as DSP. Cerquad with a window is used for packaging EPROM circuits. The heat dissipation is better than plastic QFP, and it can tolerate 1.5-2W of power under natural air cooling conditions. But the packaging cost is 3-5 times higher than plastic QFP. The pin center distances are 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and other specifications. The number of pins is from 32 to 368.
7. CLCC (ceramic leaded chip carrier)
Leaded ceramic chip carrier, one of the surface mount packaging types. The pins are led out from the four sides of the package and are in a T shape. The one with a window is used for packaging UV erasable EPROM and microcomputer circuits with EPROM, etc. This package is also called QFJ, QFJ-G (see QFJ).
8. COB (chip on board)
Chip on board packaging, one of the bare chip mounting technologies. The semiconductor chip is butt-mounted on the printed circuit board, the electrical connection between the chip and the substrate is realized by the wire stitching method, and the electrical connection between the chip and the substrate is realized by the wire stitching method, and it is covered with resin to ensure reliability. Although COB is the simplest bare chip mounting technology, its packaging density is far inferior to TAB and flip-chip soldering technologies.
9. DFP (dual flat package)
Dual flat package. Another name for SOP (see SOP). This term was previously used, but is now basically not used.
10. DIC (dual in-line ceramic package)
Another name for ceramic DIP (including glass-sealed) (see DIP).
11. DIL (dual in-line)
Another name for DIP (see DIP). European semiconductor manufacturers use this name more.
12. DIP (dual in-line package)
Dual in-line package. One of the through-hole mounting packages. The pins are led out from both sides of the package. The packaging materials are plastic and ceramic. DIP is the most popular through-hole mounting package, and its application ranges include standard logic ICs, memory LSIs, microcomputer circuits, etc. The pin center distance is 2.54mm, and the number of pins is from 6 to 64. The package width is usually 15.2mm. Some packages with a width of 7.52mm and 10.16mm are respectively called skinny DIP and slim DIP (narrow body DIP). But most of the time, they are not distinguished, and are simply collectively referred to as DIP. In addition, the ceramic DIP sealed with low-melting glass is also called cerdip (see cerdip).
13. DSO (dual small out-lint)
Another name for dual small outline package. Some semiconductor manufacturers use this name.
14. DICP (dual tape carrier package)
Dual tape carrier package. One of the TCP (tape carrier package). The pins are made on the insulating tape and led out from both sides of the package. Since TAB (automatic tape carrier welding) technology is used, the package shape is very thin. It is often used for liquid crystal display drive LSI, but most are custom products. In addition, the thin package of 0.5mm thick memory LSI is in the development stage. In Japan, according to the EIAJ (Japan Electronic Machinery Industry) association standard, DICP is named DTP.
15. DIP (dual tape carrier package)
The same as above. The name of DTCP specified by the Japan Electronic Machinery Industry Association standard (see DTCP).
16. FP (flat package)
Flat package. One of the surface mount packaging types. Another name for QFP or SOP (see QFP and SOP). Some semiconductor manufacturers use this name.
17. flip-chip
Flip-chip. One of the bare chip packaging technologies. Metal bumps are made in the electrode area of the LSI chip, and then the metal bumps are press-welded and connected with the electrode area on the printed circuit board. The occupied area of the package is basically the same as the chip size. It is the smallest and thinnest of all packaging technologies. However, if the thermal expansion coefficient of the substrate is different from that of the LSI chip, a reaction will occur at the joint, thereby affecting the reliability of the connection. Therefore, the LSI chip must be reinforced with resin, and a substrate material with a basically similar thermal expansion coefficient must be used.
18. FQFP (fine pitch quad flat package)
Fine pitch QFP. Usually refers to QFP with a pin center distance of less than 0.65mm (see QFP). Some conductor manufacturers use this name.
19. CPAC (globe top pad array carrier)
Another name for BGA by Motorola in the United States (see BGA).
20. CQFP (quad fiat package with guard ring)
Quad flat package with guard ring. One of the plastic QFPs. The pins are masked with a resin guard ring to prevent bending and deformation. Before assembling the LSI on the printed circuit board, the pins are cut from the guard ring and made into gull-wing (L shape). This package has been mass-produced by Motorola in the United States. The pin center distance is 0.5mm, and the number of pins is up to about 208.
21. H- (with heat sink)
Mark indicating with heat sink. For example, HSOP represents SOP with heat sink.
22. pin grid array (surface mount type)
Surface mount type PGA. Usually PGA is a through-hole mounting package, and the pin length is about 3.4mm. The surface mount type PGA has array-shaped pins on the bottom surface of the package, and the length is from 1.5mm to 2.0mm. The mounting is done by soldering with the printed circuit board, so it is also called butt-welded PGA. Because the pin center distance is only 1.27mm, which is half of the through-hole mounting type PGA, the package body can be made not too large, and the number of pins is more than the through-hole mounting type (250-528), which is a package for large-scale logic LSI. The base material of the package is multi-layer ceramic substrate and glass epoxy printed circuit base. The package made of multi-layer ceramic base has been put into practical use.
23. JLCC (J-leaded chip carrier)
J-leaded chip carrier. Another name for CLCC with window and ceramic QFJ with window (see CLCC and QFJ). Some semiconductor manufacturers use this name.
24. LCC (Leadless chip carrier)
Leadless chip carrier. Refers to a surface mount package with electrode contacts on the four sides of the ceramic substrate but no pins. It is a package for high-speed and high-frequency ICs, also called ceramic QFN or QFN-C (see QFN).
25. LGA (land grid array)
Land grid array package. That is, a package with array-shaped electrode contacts made on the bottom surface. It can be inserted into the socket for assembly. The practical ones are ceramic LGA with 227 contacts (1.27mm center distance) and 447 contacts (2.54mm center distance), which are applied to high-speed logic LSI circuits. Compared with QFP, LGA can accommodate more input and output pins in a relatively small package. In addition, because the impedance of the lead is small, it is suitable for high-speed LSI. However, due to the complicated production of the socket and high cost, it is basically not used much at present. It is expected that the demand for it will increase in the future.
26. LOC (lead on chip)
Lead on chip packaging. One of the LSI packaging technologies. The front end of the lead frame is in a structure above the chip. A bump is made near the center of the chip, and electrical connection is made by wire stitching. Compared with the original structure where the lead frame is arranged near the side of the chip, the chip that can be accommodated in the same size package is about 1mm wide.
27. LQFP (low profile quad flat package)
Thin QFP. Refers to a QFP with a package body thickness of 1.4mm. It is the name used by the Japan Electronic Machinery Industry Association according to the newly formulated QFP external specifications.
28. L-QUAD
One of the ceramic QFPs. The packaging substrate is made of aluminum nitride, and its thermal conductivity is 7-8 times higher than that of aluminum oxide, with better heat dissipation. The frame of the package is made of aluminum oxide, and the chip is sealed by potting method, thereby suppressing the cost. It is a package developed for logic LSI. It can tolerate W3 power under natural air cooling conditions. LSI logic packages with 208 pins (0.5mm center distance) and 160 pins (0.65mm center distance) have been developed and started mass production in October 1993.
29. MCM (multi-chip module)
Multi-chip module. A package in which multiple semiconductor bare chips are assembled on one wiring substrate. It can be divided into three categories: MCM-L, MCM-C and MCM-D according to the substrate material.
MCM-L is a component using a common glass epoxy multi-layer printed circuit board. The wiring density is not very high, and the cost is low.
MCM-C is a component that uses thick film technology to form multi-layer wiring and uses ceramic (alumina or glass ceramic) as the substrate, which is similar to the thick film hybrid IC using multi-layer ceramic substrate. There is no obvious difference between the two. The wiring density is higher than MCM-L.
MCM-D is a component that uses thin film technology to form multi-layer wiring and uses ceramic (alumina or aluminum nitride) or Si, Al as the substrate. The wiring density is the highest among the three components, but the cost is also high.
30. MFP (mini flat package)
Small flat package. Another name for plastic SOP or SSOP (see SOP and SSOP). Some semiconductor manufacturers use this name.
31. MQFP (metric quad flat package)
A classification of QFP according to the JEDEC (Joint Electronic Devices Engineering Council) standard in the United States. Refers to the standard QFP with a pin center distance of 0.65mm and a body thickness of 3.8mm-2.0mm (see QFP).
32. MQUAD (metal quad)
A QFP package developed by Olin in the United States. Both the substrate and the cover are made of aluminum, and sealed with adhesive. It can tolerate 2.5W-2.8W of power under natural air cooling conditions. Shin-Etsu Electric Industry in Japan obtained the license to start production in 1993.
33. MSP (mini square package)
Another name for QFI (see QFI). It was often called MSP in the early stage of development. QFI is the name specified by the Japan Electronic Machinery Industry Association.
34. OPMAC (over molded pad array carrier)
Molded resin sealed bump array carrier. The name used by Motorola in the United States for molded resin sealed BGA (see BGA).
35. P- (plastic)
Mark indicating plastic package. Such as PDIP represents plastic DIP.
36. PAC (pad array carrier)
Bump array carrier, another name for BGA (see BGA).
37. PCLP (printed circuit board leadless package)
Printed circuit board leadless package. The name used by Fujitsu in Japan for plastic QFN (plastic LCC) (see QFN). The pin center distances are 0.55mm and 0.4mm. It is currently in the development stage.
38. PFPF (plastic flat package)
Plastic flat package. Another name for plastic QFP (see QFP). Some LSI manufacturers use this name.
39. PGA (pin grid array)
Pin grid array package. One of the through-hole mounting packages. The vertical pins on the bottom surface are arranged in an array. The base material of the package basically uses a multi-layer ceramic substrate. In the case where the material name is not specially indicated, most are ceramic PGA, which is used in high-speed large-scale logic LSI circuits. The cost is high. The pin center distance is usually 2.54mm, and the number of pins is about 64 to 447. In order to reduce the cost, the package base material can be replaced with a glass epoxy printed circuit board. There are also plastic PGAs with 64-256 pins. In addition, there is also a short pin surface mount type PGA (butt-welded PGA) with a pin center distance of 1.27mm. (See surface mount type PGA).
40. piggy back
Piggyback package. Refers to a ceramic package with a socket, and the shape is similar to DIP, QFP, QFN. It is used for evaluating program confirmation operations when developing equipment with a microcomputer. For example, insert an EPROM into the socket for debugging. This package is basically custom-made and is not widely available on the market.
41. PLCC (plastic leaded chip carrier)
Leaded plastic chip carrier. One of the surface mount packaging types. The pins are led out from the four sides of the package and are in a T shape, which is a plastic product. Texas Instruments in the United States first used it in 64k-bit DRAM and 256kDRAM, and it has now been widely used in logic LSI, DLD (or programmable logic device) and other circuits. The pin center distance is 1.27mm, and the number of pins is from 18 to 84. The J-shaped pins are not easy to deform and are easier to operate than QFP, but the appearance inspection after soldering is more difficult. PLCC is similar to LCC (also called QFN). Previously, the difference between the two was only that the former used plastic and the latter used ceramic. But now there are J-shaped pin packages made of ceramic and leadless packages made of plastic (marked as plastic LCC, PCLP, P-LCC, etc.), which can no longer be distinguished. To this end, the Japan Electronic Machinery Industry Association decided in 1988 that the package with J-shaped pins led out from the four sides is called QFJ, and the package with electrode bumps on the four sides is called QFN (see QFJ and QFN).
42. P-LCC (plastic teadless chip carrier) (plastic leaded chip currier)
Sometimes it is another name for plastic QFJ, sometimes it is another name for QFN (plastic LCC) (see QFJ and QFN). Some LSI manufacturers use PLCC to represent leaded packages and P-LCC to represent leadless packages to distinguish them.
43. QFH (quad flat high package)
Quad flat high package. One of the plastic QFPs. In order to prevent the package body from breaking, the QFP body is made thicker (see QFP). Some semiconductor manufacturers use this name.
44. QFI (quad flat I-leaded packgac)
Quad flat I-leaded package. One of the surface mount packaging types. The pins are led out from the four sides of the package and are downward in an I shape. It is also called MSP (see MSP). The mounting is connected by soldering with the printed circuit board. Since there are no protruding parts on the pins, the mounting occupied area is smaller than QFP. Hitachi developed and used this package for video analog ICs. In addition, the PLL IC of Motorola in Japan also uses this package. The pin center distance is 1.27mm, and the number of pins is from 18 to 68.
45. QFJ (quad flat J-leaded package)
Quad flat J-leaded package. One of the surface mount packages. The pins are led out from the four sides of the package and are downward in a J shape. It is the name specified by the Japan Electronic Machinery Industry Association. The pin center distance is 1.27mm.
The materials are plastic and ceramic. Most plastic QFJs are called PLCC (see PLCC), which are used in microcomputers, gate arrays, DRAM, ASSP, OTP and other circuits. The number of pins is from 18 to 84.
Ceramic QFJ is also called CLCC, JLCC (see CLCC). The package with a window is used for UV erasable EPROM and microcomputer chip circuits with EPROM. The number of pins is from 32 to 84.
46. QFN (quad flat non-leaded package)
Quad flat non-leaded package. One of the surface mount packaging types. It is now mostly called LCC. QFN is the name specified by the Japan Electronic Machinery Industry Association. The package has electrode contacts on the four sides. Since there are no pins, the mounting occupied area is smaller than QFP, and the height is lower than QFP. However, when stress is generated between the printed circuit board and the package, it cannot be relieved at the electrode contacts. Therefore, it is difficult to make as many electrode contacts as the pins of QFP, generally from 14 to 100. The materials are ceramic and plastic. When there is an LCC mark, it is basically a ceramic QFN. The electrode contact center distance is 1.27mm.
Plastic QFN is a low-cost package with glass epoxy printed circuit board substrate. The electrode contact center distances are 1.27mm, 0.65mm and 0.5mm. This package is also called plastic LCC, PCLC, P-LCC, etc.
47. QFP (quad flat package)
Quad flat package. One of the surface mount packaging types. The pins are led out from the four sides and are in a gull-wing (L) shape. The base materials are ceramic, metal and plastic. In terms of quantity, plastic packages account for the vast majority. When the material is not specially indicated, most are plastic QFP. Plastic QFP is the most popular multi-pin LSI package. It is not only used in microprocessors, gate array and other digital logic LSI circuits, but also in analog LSI circuits such as VTR signal processing and audio signal processing. The pin center distances are 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm and other specifications. The maximum number of pins in the 0.65mm center distance specification is 304.
Japan calls QFP with a pin center distance of less than 0.65mm QFP (FP). But now the Japan Electronic Machinery Industry Association has re-evaluated the external specifications of QFP. There is no distinction based on the pin center distance, but it is divided into three types according to the package body thickness: QFP (2.0mm-3.6mm thick), LQFP (1.4mm thick) and TQFP (1.0mm thick).
In addition, some LSI manufacturers specially call QFP with a pin center distance of 0.5mm shrink QFP or SQFP, VQFP. But some manufacturers also call QFP with a pin center distance of 0.65mm and 0.4mm SQFP, causing the name to be slightly confused. The disadvantage of QFP is that when the pin center distance is less than 0.65mm, the pins are easy to bend. In order to prevent pin deformation, several improved QFP varieties have appeared. Such as BQFP with resin bumpers on the four corners of the package (see BQFP); GQFP with resin guard ring covering the front end of the pin (see GQFP); setting test bumps in the package body, and can be tested in a special fixture to prevent pin deformation TPQFP (see TPQFP). In terms of logic LSI, many development products and high-reliability products are packaged in multi-layer ceramic QFP. Products with a minimum pin center distance of 0.4mm and a maximum number of pins of 348 have also appeared. In addition, there is also a ceramic QFP sealed with glass (see Gerqa d).
48. QFP (FP) (QFP fine pitch)
Small center distance QFP. The name specified by the Japan Electronic Machinery Industry Association standard. Refers to QFP with a pin center distance of less than 0.65mm such as 0.55mm, 0.4mm, 0.3mm (see QFP).
49. QIC (quad in-line ceramic package)
Another name for ceramic QFP. Some semiconductor manufacturers use this name (see QFP, Cerquad).
50. QIP (quad in-line plastic package)
Another name for plastic QFP. Some semiconductor manufacturers use this name (see QFP).
51. QTCP (quad tape carrier package)
Quad tape carrier package. One of the TCP packages. The pins are formed on the insulating tape and led out from the four sides of the package. It is a thin package using TAB technology (see TAB, TCP).
52. QTP (quad tape carrier package)
Quad tape carrier package. The name used by the Japan Electronic Machinery Industry Association for the external specifications of QTCP formulated in April 1993 (see TCP).
53. QUIL (quad in-line)
Another name for QUIP (see QUIP).
54. QUIP (quad in-line package)
Quad in-line package. The pins are led out from both sides of the package and are staggered downward in four rows every other one. The pin center distance is 1.27mm. When inserted into the printed circuit board, the insertion center distance becomes 2.5mm. Therefore, it can be used for standard printed circuit boards. It is a package smaller than the standard DIP. NEC in Japan has used this package in microcomputer chips of desktop computers and home appliances. The materials are ceramic and plastic. The number of pins is 64.
55. SDIP (shrink dual in-line package)
Shrink dual in-line package. One of the through-hole mounting packages. The shape is the same as DIP, but the pin center distance (1.778mm) is smaller than DIP (2.54mm), so it is called this. The number of pins is from 14 to 90. It is also called SH-DIP. The materials are ceramic and plastic.
56. SH-DIP (shrink dual in-line package)
The same as SDIP. Some semiconductor manufacturers use this name.
57. SIL (single in-line)
Another name for SIP (see SIP). European semiconductor manufacturers mostly use the name SIL.
58. SIMM (single in-line memory module)
Single in-line memory module. A memory module with electrodes arranged near only one side of the printed circuit board. Usually refers to the module inserted into the socket. The standard SIMM has two specifications: 30 electrodes with a center distance of 2.54mm and 72 electrodes with a center distance of 1.27mm. SIMMs with 1-megabit and 4-megabit DRAMs packaged with SOJ on one or both sides of the printed circuit board have been widely used in devices such as personal computers and workstations. At least 30-40% of DRAMs are assembled in SIMMs.
59. SIP (single in-line package)
Single in-line package. The pins are led out from one side of the package and arranged in a straight line. When assembled on the printed circuit board, the package is in a side-standing state. The pin center distance is usually 2.54mm, and the number of pins is from 2 to 23, most of which are custom products. The shape of the package is different. Some people also call the package with the same shape as ZIP SIP.
60. SK-DIP (skinny dual in-line package)
One of the DIPs. Refers to a narrow body DIP with a width of 7.62mm and a pin center distance of 2.54mm. Usually collectively referred to as DIP (see DIP).
61. SL-DIP (slim dual in-line package)
One of the DIPs. Refers to a narrow body DIP with a width of 10.16mm and a pin center distance of 2.54mm. Usually collectively referred to as DIP.
62. SMD (surface mount devices)
Surface mount devices. Occasionally, some semiconductor manufacturers classify SOP as SMD (see SOP).
63. SO (small out-line)
Another name for SOP. Many semiconductor manufacturers in the world use this alternative name. (See SOP).
64. SOI (small out-line I-leaded package)
I-leaded small outline package. One of the surface mount packaging types. The pins are led out from both sides of the package and are downward in an I shape, with a center distance of 1.27mm. The mounting occupied area is smaller than SOP. Hitachi used this package in analog ICs (motor drive ICs). The number of pins is 26.
65. SOIC (small out-line integrated circuit)
Another name for SOP (see SOP). Many semiconductor manufacturers abroad use this name.
66. SOJ (Small Out-Line J-Leaded Package)
J-leaded small outline package. One of the surface mount packaging types. The pins are led out from both sides of the package and are downward in a J shape, hence the name. It is usually a plastic product, mostly used in memory LSI circuits such as DRAM and SRAM, but most are DRAM. Many DRAM devices packaged with SOJ are assembled on SIMMs. The pin center distance is 1.27mm, and the number of pins is from 20 to 40 (see SIMM).
67. SQL (Small Out-Line L-leaded package)
The name of SOP adopted according to the JEDEC (Joint Electronic Devices Engineering Council) standard in the United States (see SOP).
68. SONF (Small Out-Line Non-Fin)
SOP without heat sink. The same as the usual SOP. In order to distinguish it from the power IC package without heat sink, the NF (non-fin) mark is deliberately added. Some semiconductor manufacturers use this name (see SOP).
69. SOF (small Out-Line package)
Small outline package. One of the surface mount packaging types. The pins are led out from both sides of the package and are in a gull-wing shape (L shape). The materials are plastic and ceramic. It is also called SOL and DFP.
In addition to being used in memory LSIs, SOP is also widely used in relatively small ASSP and other circuits. In the field where the number of input and output terminals does not exceed 10-40, SOP is the most widely used surface mount package. The pin center distance is 1.27mm, and the number of pins is from 8 to 44.
In addition, SOP with a pin center distance of less than 1.27mm is also called SSOP; SOP with an assembly height of less than 1.27mm is also called TSOP (see SSOP, TSOP). There is also a SOP with a heat sink.
70. SOW (Small Outline Package (Wide-Jype))
Wide body SOP. Some semiconductor manufacturers use this name.

[ Last edited by zzz19760225 on 2018-9-19 at 19:14 ]