中国DOS联盟

Seven Addressing Modes (Direct Addressing Mode)
2011-06-14 13:49 by Li Longjiang, 21651 views, 0 comments, favorites, edit

The operand required by the instruction is stored in memory, and the effective address of the operand is directly given in the instruction. This addressing mode is called the direct addressing mode.

Under normal circumstances, the operand is stored in the data segment, so its physical address will be directly formed by the data segment register DS and the effective address given in the instruction. But if a segment override prefix is used, the operand can be stored in other segments.

Example: Suppose there is an instruction: MOV BX, . When executed, (DS) = 2000H, and the value of the memory unit 21234H is 5213H. What is the value of BX after this instruction is executed?

Solution: According to the addressing rules of the direct addressing mode, the specific execution process of this instruction is represented by the following figure.

From the figure, it can be seen that executing this instruction is divided into three parts:

Since 1234H is a direct address, it follows immediately after the operation code of the instruction and is read along with fetching the instruction;

The segment register for accessing the data segment is DS, so the physical address of the storage unit is obtained by adding the value of DS and the offset 1234H: 21234H;

The value 5213H of the unit 21234H is taken and stored in the register BX according to the principle of "high high and low low".

Therefore, after executing this instruction, the value of BX is 5213H.

Since the segment register of the data segment is defaulted to DS, if you want to specify to access data in other segments, you can explicitly write it in the instruction in the form of a segment prefix.

The target operand of the following instruction is a direct addressing mode with a segment prefix.

MOV ES:, AX

The direct addressing mode is often used to process data in memory units. The operand is the value of the memory variable. This addressing mode can address within a segment of 64K bytes.

Note: The writing formats of the immediate addressing mode and the direct addressing mode are different. The address of the direct addressing should be written in the parentheses "". In the program, the direct address is usually represented by a memory variable name, such as: MOV BX, VARW, where VARW is a memory word variable.

Compare the addressing modes of the source operands in the following instructions (VARW is a memory word variable):
MOV AX, 1234H MOV AX, ; The former is immediate addressing, the latter is direct addressing
MOV AX, VARW MOV AX, ; Both are equivalent, both are direct addressing

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http://www.cnblogs.com/lilongjiang/archive/2011/06/14/2080569.html


Seven Addressing Modes (Register Indirect Addressing Mode)
2011-06-14 13:57 by Li Longjiang, 7851 views, 1 comment, favorites, edit

The operand is in memory, and the effective address of the operand is specified by one of the four registers SI, DI, BX, and BP. This addressing mode is called the register indirect addressing mode. The calculation method of the physical address in this addressing mode is as follows:



The principle of reading a memory unit in the register indirect addressing mode is shown in the figure.

In the case of not using a segment override prefix, the following regulations apply:

If the effective address is specified by one of SI, DI, and BX, the default segment register is DS;
If the effective address is specified by BP, the default segment register is SS (that is, the stack segment).

Example: Suppose there is an instruction: MOV BX, . When executed, (DS) = 1000H, (DI) = 2345H, and the content of the memory unit 12345H is 4354H. What is the value of BX after executing the instruction?

Solution: According to the rules of the register indirect addressing mode, the value of register DI is not the operand when executing this example instruction, but the address of the operand. The physical address of the operand should be formed by DS and the value of DI, that is:

PA = (DS) * 16 + DI = 1000H * 16 + 2345H = 12345H.

Therefore, the execution effect of this instruction is: transfer a word value starting from the physical address 12345H to BX.

The execution process is shown in the figure.

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http://www.cnblogs.com/lilongjiang/archive/2011/06/14/2080574.html


Seven Addressing Modes (Register Relative Addressing Mode)
2011-06-14 14:01 by Li Longjiang, 6500 views, 0 comments, favorites, edit

The operand is in memory, and its effective address is the sum of the content of a base register (BX, BP) or an index register (SI, D

I) and the 8-bit/16-bit offset in the instruction. The calculation formula of its effective address is as shown in the formula.

In the case of not using a segment override prefix, the following regulations apply:

If the effective address is specified by one of SI, DI, and BX, the default segment register is DS;

If the effective address is specified by BP, the default segment register is SS.

The 8-bit/16-bit offset given in the instruction is represented by two's complement. When calculating the effective address, if the offset is 8 bits, it is sign-extended to 16 bits. When the obtained effective address exceeds 0FFFFH, take its modulo of 64K.

Example: Suppose the instruction: MOV BX, . When executing it, (DS) = 1000H, (SI) = 2345H, and the content of the memory unit 12445H is 2715H. What is the value of BX after this instruction is executed?

Solution: According to the rules of the register relative addressing mode, when executing this example instruction, the effective address EA of the source operand is:

EA = (SI) + 100H = 2345H + 100H = 2445H

The physical address of the operand should be formed by DS and EA, that is:

PA = (DS) * 16 + EA = 1000H * 16 + 2445H = 12445H.

Therefore, the execution effect of this instruction is: transfer a word value starting from the physical address 12445H to BX.

The execution process is shown in the figure.

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http://www.cnblogs.com/lilongjiang/archive/2011/06/14/2080576.html

Seven Addressing Modes (Base Plus Index Addressing Mode)
2011-06-14 14:03 by Li Longjiang, 6343 views, 0 comments, favorites, edit

The operand is in memory, and its effective address is the sum of the contents of a base register (BX, BP) and an index register (SI, DI). The calculation formula of its effective address is as shown in the formula.

In the case of not using a segment override prefix, the regulation is: If the effective address contains BP, the default segment register is SS; otherwise, the default segment register is DS.

Example: Suppose the instruction: MOV BX, . When executing, (DS) = 1000H, (BX) = 2100H, (SI) = 0011H, and the content of the memory unit 12111H is 1234H. What is the value of BX after this instruction is executed?

Solution: According to the rules of the base plus index addressing mode, when executing this example instruction, the effective address EA of the source operand is:

EA = (BX) + (SI) = 2100H + 0011H = 2111H

The physical address of the operand should be formed by DS and EA, that is:

PA = (DS) * 16 + EA = 1000H * 16 + 2111H = 12111H

Therefore, the execution effect of this instruction is: transfer a word value starting from the physical address 12111H to BX.

The execution process is shown in the figure.

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http://www.cnblogs.com/lilongjiang/archive/2011/06/14/2080576.html

Seven Addressing Modes (Base Plus Index Addressing Mode)
2011-06-14 14:03 by Li Longjiang, 6343 views, 0 comments, favorites, edit

The operand is in memory, and its effective address is the sum of the contents of a base register (BX, BP) and an index register (SI, DI). The calculation formula of its effective address is as shown in the formula.

In the case of not using a segment override prefix, the regulation is: If the effective address contains BP, the default segment register is SS; otherwise, the default segment register is DS.

Example: Suppose the instruction: MOV BX, . When executing, (DS) = 1000H, (BX) = 2100H, (SI) = 0011H, and the content of the memory unit 12111H is 1234H. What is the value of BX after this instruction is executed?

Solution: According to the rules of the base plus index addressing mode, when executing this example instruction, the effective address EA of the source operand is:

EA = (BX) + (SI) = 2100H + 0011H = 2111H

The physical address of the operand should be formed by DS and EA, that is:

PA = (DS) * 16 + EA = 1000H * 16 + 2111H = 12111H

Therefore, the execution effect of this instruction is: transfer a word value starting from the physical address 12111H to BX.

The execution process is shown in the figure.

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http://www.cnblogs.com/lilongjiang/archive/2011/06/14/2080581.html

Seven Addressing Modes (Relative Base Plus Index Addressing Mode)
2011-06-14 14:07 by Li Longjiang, 5701 views, 0 comments, favorites, edit

The operand is in memory, and its effective address is the sum of the value of a base register (BX, BP), the value of an index register (SI, DI), and the 8-bit/16-bit offset in the instruction. The calculation formula of its effective address is as shown in the formula.

In the case of not using a segment override prefix, the regulation is: If the effective address contains BP, the default segment register is SS; otherwise, the default segment register is DS.

The 8-bit/16-bit offset given in the instruction is represented by two's complement. When calculating the effective address, if the offset is 8 bits, it is sign-extended to 16 bits. When the obtained effective address exceeds 0FFFFH, take its modulo of 64K.

Example: Suppose the instruction: MOV AX, . When executing, (DS) = 1000H, (BX) = 2100H, (SI) = 0010H, and the content of the memory unit 12310H is 1234H. What is the value of AX after this instruction is executed?

Solution: According to the rules of the relative base plus index addressing mode, when executing this example instruction, the effective address EA of the source operand is:

EA = (BX) + (SI) + 200H = 2100H + 0010H + 200H = 2310H

The physical address of the operand should be formed by DS and EA, that is:

PA = (DS) * 16 + EA = 1000H * 16 + 2310H = 12310H

Therefore, the execution effect of this instruction is: transfer a word value starting from the physical address 12310H to AX. The execution process is shown in the figure.

From the perspective of the relative base plus index addressing mode, since it has more variable factors, it seems more complicated. But precisely because it has more variable factors, its flexibility is also very high. For example:

Use D1 to access the i-th element of one-dimensional array D1. Its addressing has one degree of freedom. Use D2 to access the element of the i-th row and j-th column of two-dimensional array D2. Its addressing has two degrees of freedom. One more variable quantity increases the flexibility of the addressing mode accordingly.

There are multiple equivalent writing methods for the relative base plus index addressing mode. The following writing formats are all correct, and their addressing meanings are also consistent.

MOV AX, 　　　MOV AX, 1000H
MOV AX, 1000H　　　 MOV AX, 1000H

But writing formats such as BX and SI are incorrect, that is, the used register cannot be outside "". This restriction also applies to the writing of the register relative addressing mode.

The relative base plus index addressing mode is the most complex addressing mode among the above 7 addressing modes. It can be transformed into other types of memory addressing modes. The following table lists the transformation relationships between this addressing mode and other addressing modes.

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http://www.cnblogs.com/lilongjiang/archive/2011/06/14/2080588.html

Seven Addressing Modes (32-bit Address Addressing Mode)
2011-06-14 14:10 by Li Longjiang, 2609 views, 0 comments, favorites, edit

In a 32-bit microcomputer system, in addition to supporting the above seven addressing modes, a more flexible, convenient but also more complex memory addressing mode is provided, thereby further expanding the addressing range of memory addresses.

When using 16-bit registers to access memory units, only the base address registers (BX and BP) and index registers (SI and DI) can be used as part of the address offset. But when using 32-bit registers for addressing, there is no above restriction. All 32-bit registers (EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP) can be a component of the address offset.

When addressing with a 32-bit address offset, the offset of the memory address can be divided into three parts: a 32-bit base register, a 32-bit index register that can be multiplied by 1, 2, 4, or 8, and an 8-bit/32-bit offset constant, and these three parts can also be arbitrarily combined, omitting one or two of them.

32-bit base registers are: EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP;
32-bit index registers are: EAX, EBX, ECX, EDX, ESI, EDI, and EBP (except ESP).

The following lists several 32-bit address addressing instructions:

MOV AX,
MOV EAX,
MOV EBX,
MOV EBX,
MOV EDX,
MOV EBX,
MOV EBX,
MOV AX,

The calculation formula of the effective address for addressing with a 32-bit address offset is summarized as shown in the formula.



Since the 32-bit addressing mode can use all general-purpose registers, the segment registers combined with the effective address also have new regulations. The specific regulations are as follows:

1. The writing order of registers in the address determines whether the register is a base register or an index register;

For example: In , EBX is the base register and EBP is the index register, while in , EBP is the base register and EBX is the index register;

2. The selection of the default segment register depends on the base register;

3. When the base register is EBP or ESP, the default segment register is SS; otherwise, the default segment register is DS;

4. In the instruction, if the segment prefix method is used, then the explicit segment register has priority.

The following lists several 32-bit address addressing instructions and the segment registers of their memory operands.

Instruction example Segment register used to access memory units
MOV AX, ；Default segment register DS
MOV EAX, ；Default segment register DS
MOV EBX, ；Default segment register SS
MOV EBX, ；Default segment register DS
MOV EDX, ES: ；Explicit segment register ES
MOV , AX ；Default segment register SS
MOV EBX, GS: ；Explicit segment register GS
MOV AX, ；Default segment register SS

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http://www.cnblogs.com/lilongjiang/archive/2011/06/15/2081124.html

Register Table
2011-06-15 07:55 by Li Longjiang, 1167 views, 2 comments, favorites, edit
http://www.cnblogs.com/del/archive/2008/01/31/1059880.html Transferred from Wanyi's blog

Type Name Binary code Register description
Multi-functional register AL 0 Low eight bits of accumulator register
AH 100 Low eight bits of accumulator register
AX 0 16-bit accumulator register
EAX 0 32-bit accumulator register
BL 11 Low eight bits of base register
BH 111 Low eight bits of base register
BX 11 16-bit base register
EBX 11 32-bit base register
CL 1 Low eight bits of count register
CH 101 Low eight bits of count register
CX 1 16-bit count register
ECX 1 32-bit count register
DL 10 Low eight bits of data register
DH 110 Low eight bits of data register
DX 10 16-bit data register
EDX 10 32-bit data register
Pointer register SP 100 16-bit stack pointer register
ESP 100 32-bit stack pointer register
BP 101 16-bit base pointer register
EBP 101 32-bit base pointer register
Index register DI 111 16-bit destination index register
EDI 111 32-bit destination index register
SI 110 16-bit source index register
ESI 110 32-bit source index register
Special register IP * 16-bit instruction pointer register
EIP * 32-bit instruction pointer register
FLAGS * 16-bit flag register
EFLAGS * 32-bit flag register
Segment register CS 1 Code segment register
DS 11 Data segment register
ES 0 Extra segment register
SS 10 Stack segment register
FS 100 Flag segment register
GS 101 Global segment register
Control register CR0 0 Control register zero
CR1* 1 Control register one
CR2 10 Control register two
CR3 11 Control register three
CR4 100 Control register four
CR5* 101 Control register five
CR6* 110 Control register six
CR7* 111 Control register seven
Debug register DR0 0 Debug register zero
DR1 1 Debug register one
DR2 10 Debug register two
DR3 11 Debug register three
DR4* 100 Debug register four
DR5* 101 Debug register five
DR6 110 Debug register six
DR7 111 Debug register seven
Task register TR0 0 Task register zero
TR1 1 Task register one
TR2 10 Task register two
TR3 11 Task register three
TR4 100 Task register four
TR5 101 Task register five
TR6 110 Task register six
TR7 111 Task register seven
Floating-point register ST0 0 Floating-point register zero
ST1 1 Floating-point register one
ST2 10 Floating-point register two
ST3 11 Floating-point register three
ST4 100 Floating-point register four
ST5 101 Floating-point register five
ST6 110 Floating-point register six
ST7 111 Floating-point register seven
Multimedia register MM0 0 Media register zero
MM1 1 Media register one
MM2 10 Media register two
MM3 11 Media register three
MM4 100 Media register four
MM5 101 Media register five
MM6 110 Media register six
MM7 111 Media register seven
Single instruction stream, multiple data stream register XMM0 0 Single instruction stream, multiple data stream register zero
XMM1 1 Single instruction stream, multiple data stream register one
XMM2 10 Single instruction stream, multiple data stream register two
XMM3 11 Single instruction stream, multiple data stream register three
XMM4 100 Single instruction stream, multiple data stream register four
XMM5 101 Single instruction stream, multiple data stream register five
XMM6 110 Single instruction stream, multiple data stream register six
XMM7 111 Single instruction stream, multiple data stream register seven
Note: The English name with an asterisk "*" means it is a reserved field and is not actually used. The binary code with an asterisk "*" means no binary number needs to be represented

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http://www.cnblogs.com/lilongjiang/archive/2011/06/15/2081128.html

Assembly Instruction Quick Reference
2011-06-15 08:01 by Li Longjiang, 544 views, 0 comments, favorites, edit
http://www.cnblogs.com/del/archive/2010/03/16/1687665.html Transferred from Wanyi's blog

Instruction Function
AAA Adjust addition
AAD Adjust division
AAM Adjust multiplication
AAS Adjust subtraction
ADC Carry addition
ADD Add
AND And
ARPL Adjust priority
BOUND Check array
BSF Bit right scan
BSR Bit left scan
BSWAP Swap bytes
BT Bit test
BTC Bit test and invert
BTR Bit test and clear
BTS Bit test and set
CALL Procedure call
CBW Convert byte
CDQ Convert double word
CLC Clear carry
CLD Clear direction
CLI Clear interrupt
CLTS Task clear
CMC Complement carry
CMOVA Transfer if above
CMOVB Transfer if below
CMOVE Transfer if equal
CMOVG Transfer if greater
CMOVL Transfer if less
CMOVNA Transfer if not above
CMOVNB Transfer if not below
CMOVNE Transfer if not equal
CMOVNG Transfer if not greater
CMOVNL Transfer if not less
CMOVNO Transfer if not overflow
CMOVNP Transfer if not parity
CMOVNS Transfer if not sign
CMOVO Transfer if overflow
CMOVP Transfer if parity
CMOVS Transfer if sign
CMP Compare
CMPSB Compare byte string
CMPSD Compare double word string
CMPSW Compare word string
CMPXCHG Compare and exchange
CMPXCHG486 Compare and exchange 486
CMPXCHG8B Compare and exchange 8 bytes
CPUID CPU identification
CWD Convert word
CWDE Extend word
DAA Adjust addition decimal
DAS Adjust subtraction decimal
DEC Decrement by one
DIV Divide
ENTER Establish stack frame
HLT Halt
IDIV Signed divide
IMUL Signed multiply
IN Port input
INC Increment by one
INSB Port input byte string
INSD Port input double word string
INSW Port input word string
JA Jump if above
JB Jump if below
JBE Jump if not above
JCXZ Jump if CX is zero
JE Jump if equal
JECXZ Jump if ECX is zero
JG Jump if greater
JL Jump if less
JMP Jump
JMPE Jump extend
JNB Jump if not below
JNE Jump if not equal
JNG Jump if not greater
JNL Jump if not less
JNO Jump if not overflow
JNP Jump if not parity
JNS Jump if not sign
JO Jump if overflow
JP Jump if parity
JS Jump if sign
LAHF Load flag low eight
LAR Load access permission
LDS Load data segment
LEA Load effective address
LEAVE Clear procedure stack
LES Load extra segment
LFS Load flag segment
LGDT Load global descriptor
LGS Load global segment
LIDT Load interrupt descriptor
LMSW Load status word
LOADALL Load all
LOADALL286 Load all 286
LOCK Lock
LODSB Load source index byte string
LODSD Load source index double word string
LODSW Load source index word string
LOOP Loop
LOOPE Loop if equal
LOOPNE Loop if not equal
LOOPNZ Loop if not zero
LOOPZ Loop if zero
LSL Load segment limit
LSS Load stack segment
LTR Load task
MONITOR Monitor
MOV Move
MOVSB Move byte string
MOVSD Move double word string
MOVSW Move word string
MOVSX Sign extend move
MOVZX Zero extend move
MUL Multiply
MWAIT
NEG Negate
NOP No operation
NOT Not
OR Or
OUT Port output
OUTSB Port output byte string
OUTSD Port output double word string
OUTSW Port output word string
POP Pop
POPA Pop all
POPF Pop flag
PUSH Push
PUSHA Push all
PUSHF Push flag
RCL Rotate left through carry
RCR Rotate right through carry
RDMSR Read special model
RDPMC Read execution monitor count
RDSHR
RDTSC Read time stamp count
REP Repeat
REPE Repeat if equal
REPNE Repeat if not equal
RET Procedure return
RETF Far procedure return
RETN Near procedure return
ROL Rotate left
ROR Rotate right
RSM Restore system management
SAHF Store flag low eight
SAL Arithmetic left shift
SALC
SAR Arithmetic right shift
SBB Borrow subtract
SCASB Scan byte string
SCASD Scan double word string
SCASW Scan word string
SETA Set if above
SETB Set if below
SETE Set if equal
SETG Set if greater
SETL Set if less
SETNA Set if not above
SETNB Set if not below
SETNE Set if not equal
SETNG Set if not greater
SETNL Set if not less
SETNO Set if not overflow
SETNP Set if not parity
SETNS Set if not sign
SETO Set if overflow
SETP Set if parity
SETS Set if sign
SGDT Save global descriptor
SHL Shift left logical
SHLD Shift left double precision
SHR Shift right logical
SHRD Shift right double precision
SIDT Save interrupt descriptor
SLDT Save local descriptor
SMI
SMINT
SMINTOLD
SMSW Save status word
STC Set carry
STD Set direction
STI Set interrupt
STOSB Store byte string
STOSD Store double word string
STOSW Store word string
STR Store task
SUB Subtract
SYSCALL System call
SYSENTER System enter
SYSEXIT System exit
SYSRET System return
TEST Test number
UD0 Undefined instruction 0
UD1 Undefined instruction 1
UD2 Undefined instruction 2
UMOV
VERW Verify write
WAIT Wait
WBINVD Write back invalidate cache
WRMSR Write special model
WRSHR
XADD Exchange and add
XBTS
XCHG Exchange
XLAT Translate
XOR Exclusive or
XSTORE


Instruction Function
EMMS Media empty MMX state
F2XM1 Absolute value of top of floating-point stack
FADD Floating-point add
FADDP Floating-point add and pop
FBLD Floating-point load ten number
FBSTP Floating-point save ten number and pop
FCHS Floating-point sign invert
FCLEX Floating-point error clear
FCMOVB Floating-point transfer if below
FCMOVBE Floating-point transfer if not above
FCMOVE Floating-point transfer if equal
FCMOVNB Floating-point transfer if not below
FCMOVNBE Floating-point transfer if above
FCMOVNE Floating-point transfer if not equal
FCMOVNU Floating-point transfer if ordered
FCMOVU Floating-point transfer if unordered
FCOM Floating-point compare
FCOMI Floating-point compare and load flag
FCOMIP Floating-point compare and load flag and pop
FCOMP Floating-point compare and pop
FCOMPP Floating-point compare and pop two
FCOS Floating-point cosine
FDECSTP Floating-point stack pointer decrement by one
FDISI Floating-point check disable interrupt
FDIV Floating-point divide
FDIVP Floating-point divide and pop
FDIVR Floating-point reciprocal divide
FDIVRP Floating-point reciprocal divide and pop
FENI Floating-point check enable interrupt
FFREE Floating-point free
FFREEP Floating-point free and pop
FIADD Floating-point add integer
FICOM Floating-point compare integer
FICOMP Floating-point compare integer and pop
FIDIV Floating-point divide integer
FIDIVR Floating-point reciprocal divide integer
FILD Floating-point load integer
FIMUL Floating-point multiply integer
FINCSTP Floating-point stack pointer increment by one
FINIT Floating-point initialize
FIST Floating-point save integer
FISTP Floating-point save integer and pop
FISTTP 　
FISUB Floating-point subtract integer
FISUBR Floating-point reciprocal subtract integer
FLD Floating-point load number
FLD1 Floating-point load one
FLDCW Floating-point load control word
FLDENV Floating-point load environment
FLDL2E Floating-point load L2E
FLDL2T Floating-point load L2T
FLDLG2 Floating-point load LG2
FLDLN2 Floating-point load LN2
FLDPI Floating-point load PI
FLDZ Floating-point load zero
FMUL Floating-point multiply
FMULP Floating-point multiply and pop
FNCLEX Floating-point no error clear
FNDISI Floating-point no check disable interrupt
FNENI Floating-point no check enable interrupt
FNINIT Floating-point no initialize
FNOP Floating-point no operation
FNSAVE Floating-point no save state
FNSTCW Floating-point no save control word
FNSTENV Floating-point no save environment
FNSTSW Floating-point no save status word
FPATAN Floating-point partial arctangent
FPREM Floating-point partial remainder
FPREM1 Floating-point partial remainder two
FPTAN Floating-point partial tangent
FRNDINT Floating-point round and integer
FRSTOR Floating-point restore state
FSAVE Floating-point save state
FSCALE Floating-point scale operation
FSETPM Floating-point set protection
FSIN Floating-point sine
FSINCOS Floating-point sine and cosine
FSQRT Floating-point square root
FST Floating-point save
FSTCW Floating-point save control word
FSTENV Floating-point save environment
FSTP Floating-point save and pop
FSTSW Floating-point save status word
FSUB Floating-point subtract
FSUBP Floating-point subtract and pop
FSUBR Floating-point reciprocal subtract
FSUBRP Floating-point reciprocal subtract and pop
FTST Floating-point compare with zero
FUCOM Floating-point unordered compare
FUCOMI Floating-point unordered compare and load flag
FUCOMIP Floating-point unordered compare and load flag and pop
FUCOMP Floating-point unordered compare and pop
FUCOMPP Floating-point unordered compare and pop two
FWAIT Floating-point wait
FXAM Floating-point examine
FXCH Floating-point exchange
FXTRACT Floating-point extract
FYL2X Floating-point compute L2X
FYL2XP1 Floating-point compute L2XP1
MOVED Media double word move
MOVEQ Media four word move
PACKSSDW Media signed double word pack
PACKSSWB Media signed word pack
PACKUSWB Media unsigned word pack
PADDB Media truncated byte add
PADDD Media truncated double word add
PADDSB Media signed saturated byte add
PADDSIW 　
PADDSW Media signed saturated word add
PADDUSB Media unsigned saturated byte add
PADDUSW Media unsigned saturated word add
PADDW Media truncated word add
PAND Media and
PANDN Media and not
PAVEB 　
PCMPEQB Media byte compare equal
PCMPEQD Media double word compare equal
PCMPEQW Media word compare equal
PCMPGTB Media byte compare greater
PCMPGTD Media double word compare greater
PCMPGTW Media word compare greater
PDISTIB 　
PMACHRIW 　
PMADDWD 　
PMAGW 　
PMULHRIW 　
PMULHRWC 　
PMULHW 　
PMVGEZB 　
PMVLZB 　
PMVNZB 　
PMVZB 　
POR Media or
PSLLD Media double word left shift
PSLLQ Media four word left shift
PSLLW Media word left shift
PSRAD Media double word arithmetic right shift
PSRAW Media word arithmetic right shift
PSRLD Media double word right shift
PSRLQ Media four word right shift
PSRLW Media word right shift
PSUBB Media truncated byte subtract
PSUBSB Media signed saturated byte subtract
PSUBSIW 　
PSUBSW Media signed saturated word subtract
PSUBUSB Media unsigned saturated byte subtract
PSUBUSW Media unsigned saturated word subtract
PSUBW Media truncated word subtract
PUNPCKHBW Media byte high unpack
PUNPCKHDQ Media double word high unpack
PUNPCKHWD Media word high unpack
PUNPCKLBW Media byte low unpack
PUNPCKLDQ Media double word low unpack
PUNPCKLWD Media word low unpack

Last edited by zzz19760225 on 2016-12-12 at 15:24 ]