EP2C8 FPGA开发板 SOPC开发板V5.0
具体介绍:
http://www.yheda.com/Shop/fpga/altera/200809/107.html
FPGA开发,SOPC开发,Nios开发的最佳选择
V5系列是在V3的基础上,把flash由V3的2MByte统一升级为8Mbyte,V5实验板在V3的基础上,
增加了两个4位数码管,10M网络功能,A/D转换,以及D/A转换,同时学习例程更丰富。
注:套件都是以核心板+实验板组合的方式
以上价格均不含发票,开发票需另加6%税点
我们秉承一贯以来实用的理念,处处用心为用户着想,5.0版本在3.0版本的基础上,重新精心
打造,每个功能都精心设计实用的例子程序,并重新编写详细的教程,无论用于学习或是研制
产品原型,都非常具有实际意义。另外我们设计了包含Cyclone、CycloneII等多款核心板供用
户选择,不断开发和供应各种实用的功能扩展板,扩展性能卓越。无论学习、开发,该套件都
是您合适的首选。
质量保证:
(1)我们竭诚为顾客提供超值的产品。任何产品邮发之前都经过严格的检验和测试,保证每
个功能都工作良好。如果有质量问题,7天内免费更换,一年保修,对于人为造成的损坏(如
使用不当烧毁芯片等),我们仍给以免费维修,但需以成本价收取芯片费用。
(2)于外地客户,我们采用信誉良好的航空快递公司进行配送,保证产品快速完好地送到客
户手上,如果在配送过程中有损坏,我们负责给予更换。
(3)我们严格控制产品出厂的质量,做到每块板卡邮出之前经过再三测试,如遇特殊情况,
请及时联系我们,我们会给予精诚的解决方案。我们视质量和服务是我们获得顾客长期信赖
和合作的根本,更是我们赖之成长的源泉。
技术支持:采用电话、BBS、QQ、QQ客户群等方式。
套件包括:
一、 FPGA核心板:多种核心板供选择(各核心板资料及图片请查看本站网上商城页面),所
采用的FPGA分别有:
(1)Cyclone核心:EP1C12Q240C8、EP1C6Q240C8;
(2)CycloneII核心:EP2C8Q208C8、EP2C5Q208C8、EP2C20Q208C8;
CycloneIII核心:EP3C16Q240C8、EP3C25Q240C8;
(3)SDRAM:8MByte;
(4)Flash:8MByte;
(5)EPCS1或EPCS4配置芯片:EP1C6和EP2C5核心板配备EPCS1;EP1C12和EP2C8以及EP2C20
核心板配备EPCS4;
(6)提供配置模式:JTAG和AS。此外配置管脚通过插针引出,可支持用户今后设计使用
PLD+Flash的配置模式;
(7)50Mhz有源时钟;
(8)所有IO、Avalon总线、配置管脚等都通过4排插针引出,用户可以充分自由发挥,扩
展更灵活;
(9)4个LED;
(10)一个reset按钮。
二、实验板V5.0配备:
★10M以太网络接口:使用RTL8019芯片;
★8位AD模数转换器;
★4通道8位DA数模转换器;
★实时时钟;
★RS-232串口:用于与计算机的数据通信;
★VGA接口:直接VGA与显示器对接,用FPGA实现VGA接口协议可在显示器上显示文字、图
型等。
★PS/2鼠标、键盘接口。
★16*2字符型LCD接口,可以显示英文字符 。
★128*64点阵式LCD接口,可以显示中文、图形等;
★蜂鸣器。
★USB接口:
采用USB-UART桥接芯片CP2102,兼容USB1.1和USB2.0协议,最高通信速率为1Mbps,可直
接用于通信速率要求不是很高的场合,如工控设备、仪器仪表等,方便实用;开发者无需懂
得USB协议和设计驱动程序,只需类似串口一样对通讯进行操作即可,因而使得开发周期短,
风险小,成本低;另外,它体积小,抗干扰性能好,工作稳定可靠,正常工作温度范围为:
-40~+85℃。随套件的光碟中,附带了该芯片的数据手册、驱动程序,以及例子程序。
★两个4位7段数码管。
★基于I2C协议的EEPROM存储器。
★4个按键开关:同样秉承简约风格,不追求多,但求简约,节省有限的IO资源,用于NiosII
的外部按键输入、中断等实验足矣
三、 ByteBlasterII下载线,如需换成USB-Blaster下载线(完全兼容Altera原装USB-Blaster)
需另加120元。
四、其它附件:
(1)16x2型LCD模块,选配,仅需20元;
(2)128x64点阵型LCD模块,选配,仅需80元;
(3)USB2.0扩展模块,选配,380元;
特别说明:我们的所有例子源码并非仅仅是Altera网站上提供的范例代码,所有例子
代码均为我们工程师的辛苦劳动所得,实在而好用。这些代码经由我们工程师的精心
调试,在每个型号上都调试通过。这些例子不仅仅用于学习,更可直接用于实际应用中。
五、配套清单
V5套件配套清单:
(1)、核心板一块;
(2)、实验板一块;
(3)、ByteBlasterII下载线一根
(4)、USB线一根;
(5)、5V开关电源一个;
(6)、DVD光盘一张包含齐全的软件(QuartusII7.2和NiosII IDE7.2版等)、实验
手册、文档资料等以及详尽电路原理图(pdf格式);提供FPGA等芯片的protel格式
元件封装图。
FPGA实验:
FPGA实验我们同时提供VHDL和Verilog HDL两种语言编写例子工程。
实验包含有:
(1)、FPGA_LED;
(2)、4位7段动态扫描数码管显示;
(3)、PS2键盘接口电路设计;
(4)、蜂鸣器奏乐实验;
(5)、LCD显示实验;
(6)、UART串口通信实验;
(7)、VGA信号发生器实验;
(8)、I2C总线的EEPROM读写;
(9)、AD转换数据采集实验;
(10)、DA数模转换实验;
SOPC实验:
Altera的FPGA特色在于基于NiosII核的SOPC系统的完善与强大性,Altera提供大量
用于Nios系统的免费IP核,以及完善的API驱动函数。使我们开发SOPC系统更加的方
便和简单。
提供的SOPC实验有:
(1)、SOPC_LED:一个最简单的Nios系统实验。
(2)、SOPC_LED_BF:Flash烧写实验。
(3)、定时器中断实验;
(4)、按键中断实验;
(5)、DMA传输实验;
(6)、UART串口通信实验;
(7)、脉宽调制PWM实验;
(8)、PS2键盘实验;
(9)、利用定时器中断产生不同频率驱动蜂鸣器奏乐实验;
(10)、LCD1602显示实验,提供HAL API驱动函数,标准C库函数访问。
(11)、LCD12864液晶屏显示实验,提供完整驱动函数,使用方便。
(12)、(12)、VGA显示实验,使用DMA传输,在显示器上显示8色320*240分辨率的
英文,汉字,图片,动画等。
(13)、实时时钟芯片PCF8563使用实验。
(14)、I2C接口的EEPROM存储器读写实验。
(15)、网络通信实验:提供一个simple_socket_server远程登陆实验,以及一个Web
server网络服务器实验;
(16)、AD数据采集实验;
(17)、DA数模转换实验;
(18)、基于avalon总线的自定义外设数码管接口设计;
(19)、自定义指令实验;
(20)、浮点指令使用实验;
(21)、双NiosII CPU核实验;
(22)、UCOSII操作系统实验;
(23)、Uclinux操作系统移植实验(注:提供基于QII5.1的移植教程,QII7.2需要在
Linux操作系统下完成移植,本站仅提供参考文档);
(24)、提供8051单片机核移植到FPGA教程与例子工程,喜欢8051的朋友在FPGA上依然
可以继续玩一把。
软件QII7.2版本比以前的版本做了很大的改动,以前的教程资料对于7.2版本很多已不
太适用。为避免初学者走过多的弯路,我们的文档都是基于7.2版本下重新编写。并且
争对初学者编写几个详尽的实验教程,一步步领导初学者快速撑握FPGA、SOPC的应用开
发。
FPGA_LED:用一个按键控制一个LED的亮灭。一个最简单的实验,让初学者熟悉QII软件
的使用,掌握FPGA的开发流程,文档中图文并茂,详细描述各步骤以及注意事项,让初
学者轻松入门FPGA的开发。
FPGA_74SEG:设计一个动态4位数码管显示电路以及波形仿真实验,让初学者由浅入深逐
渐深入FPGA的开发,学习和掌握使用QII的进行电路仿真。
SOPC_LED:设计一个最简单的SOPC系统,由NiosII CPU+片上存储器+LED组成,学习SOPC
开发的基本流程,学习SOPC Builder基本使用以及Nios集成开发环境(NiosIDE)下C程序
的编写和在线调试。
SOPC_LED_BF:往SOPC系统中添加SDRAM控制器,Flash控制器,学习SDRAM和Flash的使用方
法,把调试好的程序烧写到flash中,上电后程序自动下载到SDRAM中执行。
EP1C12型:880元/套(购买型号:T1C12-V5)
EP2C5型:730元/套(购买型号:T2C5-V5)
EP2C8型:860元/套(购买型号:T2C8-V5)
EP3C25型:1260元/套(购买型号:T3C25-V5)
运费:20元
购买方式:
http://www.yheda.com/Article/ShowArticle.asp?ArticleID=8409
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EP2C8 FPGA Development Board SOPC Development Board V5.0
Specific introduction:
http://www.yheda.com/Shop/fpga/altera/200809/107.html
The best choice for FPGA development, SOPC development, and Nios development
The V5 series is an upgrade from the V3 series, uniformly upgrading the flash from 2MByte in V3 to 8Mbyte. The V5 experimental board adds two 4-bit digital tubes, 10M network function, A/D conversion, and D/A conversion on the basis of V3, and the learning examples are more abundant.
Note: The kits are all in the form of a core board + experimental board combination
The above prices do not include invoices. An additional 6% tax point is required for invoicing.
We adhere to the concept of practicality all the time, and consider users' needs everywhere. The 5.0 version is carefully crafted on the basis of the 3.0 version. Each function is carefully designed with practical example programs, and detailed tutorials are rewritten. It is very meaningful whether for learning or developing product prototypes. In addition, we design multiple core boards including Cyclone, Cyclone II, etc. for users to choose from, and continuously develop and supply various practical function expansion boards with excellent expansion performance. Whether for learning or development, this kit is a suitable first choice for you.
Quality assurance:
(1) We are committed to providing customers with cost-effective products. Any product is strictly inspected and tested before mailing to ensure that each function works well. If there is a quality problem, it will be replaced free of charge within 7 days, and it is guaranteed for one year. For damage caused by human factors (such as burning the chip due to improper use, etc.), we will still provide free repair, but the chip cost will be charged at cost price.
(2) For customers from other places, we use a well-known air express company for delivery to ensure that the product is delivered to the customer quickly and intactly. If there is damage during delivery, we are responsible for replacement.
(3) We strictly control the quality of the product before leaving the factory, and do three tests on each board before mailing. In case of special circumstances, please contact us in time, and we will give a sincere solution. We regard quality and service as the foundation for customers' long-term trust and cooperation, and also the source of our growth.
Technical support: Methods such as telephone, BBS, QQ, QQ customer groups, etc. are adopted.
The kit includes:
1. FPGA core board: multiple core boards for selection (for information and pictures of each core board, please check the online mall page of this site). The FPGAs used are:
(1) Cyclone core: EP1C12Q240C8, EP1C6Q240C8;
(2) Cyclone II core: EP2C8Q208C8, EP2C5Q208C8, EP2C20Q208C8; Cyclone III core: EP3C16Q240C8, EP3C25Q240C8;
(3) SDRAM: 8MByte;
(4) Flash: 8MByte;
(5) Configuration chip EPCS1 or EPCS4: EP1C6 and EP2C5 core boards are equipped with EPCS1; EP1C12, EP2C8 and EP2C20 core boards are equipped with EPCS4;
(6) Provide configuration modes: JTAG and AS. In addition, the configuration pins are led out through pin headers, which can support the user's future design and use of the PLD + Flash configuration mode;
(7) 50Mhz active clock;
(8) All IO, Avalon bus, configuration pins, etc. are led out through 4-row pin headers, allowing users to give full play and expand more flexibly;
(9) 4 LEDs;
(10) One reset button.
2. The experimental board V5.0 is equipped with:
★10M Ethernet interface: using RTL8019 chip;
★8-bit AD analog-to-digital converter;
★4-channel 8-bit DA digital-to-analog converter;
★Real-time clock;
★RS-232 serial port: used for data communication with the computer;
★VGA interface: directly connect VGA to the display, and use FPGA to implement the VGA interface protocol to display text, graphics, etc. on the display.
★PS/2 mouse and keyboard interface.
★16*2 character LCD interface, which can display English characters.
★128*64 dot matrix LCD interface, which can display Chinese, graphics, etc.;
★Buzzer.
★USB interface:
Adopt USB-UART bridge chip CP2102, compatible with USB1.1 and USB2.0 protocols, with a maximum communication rate of 1Mbps, which can be directly used in occasions where the communication rate is not very high, such as industrial control equipment, instrument meters, etc., which is convenient and practical; developers do not need to understand the USB protocol and design the driver program, just operate the communication like a serial port, thus making the development cycle short, the risk small, and the cost low; in addition, it is small in size, good in anti-interference performance, stable and reliable in work, and the normal working temperature range is: -40 ~ +85°C. In the CD of the kit, the data sheet, driver program, and example program of this chip are attached.
★Two 4-bit 7-segment digital tubes.
★EEPROM memory based on I2C protocol.
★4 button switches: also adhering to the simple style, not pursuing many, but seeking simplicity, saving limited IO resources, which is enough for experiments such as external button input and interrupt of Nios II.
3. ByteBlasterII download cable. If you need to replace it with a USB-Blaster download cable (fully compatible with Altera original USB-Blaster), an additional 120 yuan is required.
4. Other accessories:
(1) 16x2 LCD module, optional, only 20 yuan;
(2) 128x64 dot matrix LCD module, optional, only 80 yuan;
(3) USB2.0 expansion module, optional, 380 yuan;
Special note: All our example source codes are not just the sample codes provided on the Altera website. All example codes are the hard work of our engineers, practical and easy to use. These codes have been carefully debugged by our engineers and tested on each model. These examples are not only for learning, but can also be directly used in actual applications.
5. Supporting list
V5 kit supporting list:
(1) One core board;
(2) One experimental board;
(3) One ByteBlasterII download cable;
(4) One USB cable;
(5) One 5V switching power supply;
(6) One DVD disc containing complete software (QuartusII7.2 and NiosII IDE7.2 version, etc.), experimental manual, document data, etc., as well as detailed circuit schematic (pdf format); provide Protel format component package diagrams of FPGA and other chips.
FPGA experiments:
For FPGA experiments, we provide example projects written in both VHDL and Verilog HDL languages.
The experiments include:
(1) FPGA_LED;
(2) 4-bit 7-segment dynamic scanning digital tube display;
(3) PS2 keyboard interface circuit design;
(4) Buzzer music playing experiment;
(5) LCD display experiment;
(6) UART serial communication experiment;
(7) VGA signal generator experiment;
(8) I2C bus EEPROM reading and writing;
(9) AD conversion data acquisition experiment;
(10) DA digital-to-analog conversion experiment;
SOPC experiments:
The feature of Altera's FPGA lies in the perfection and power of the SOPC system based on the Nios II core. Altera provides a large number of free IP cores for the Nios system and complete API driver functions. This makes our development of the SOPC system more convenient and simple.
The provided SOPC experiments are:
(1) SOPC_LED: the simplest Nios system experiment.
(2) SOPC_LED_BF: Flash burning experiment.
(3) Timer interrupt experiment;
(4) Button interrupt experiment;
(5) DMA transmission experiment;
(6) UART serial communication experiment;
(7) Pulse width modulation PWM experiment;
(8) PS2 keyboard experiment;
(9) Using timer interrupt to generate different frequencies to drive the buzzer to play music experiment;
(10) LCD1602 display experiment, providing HAL API driver functions and standard C library function access.
(11) LCD12864 liquid crystal display experiment, providing complete driver functions and easy to use.
(12) (12) VGA display experiment, using DMA transmission, displaying English, Chinese characters, pictures, animations, etc. with 8 colors and 320*240 resolution on the display.
(13) Real-time clock chip PCF8563 use experiment.
(14) I2C interface EEPROM memory reading and writing experiment.
(15) Network communication experiment: providing a simple_socket_server remote login experiment, and a Web server network server experiment;
(16) AD data acquisition experiment;
(17) DA digital-to-analog conversion experiment;
(18) Custom peripheral digital tube interface design based on the Avalon bus;
(19) Custom instruction experiment;
(20) Floating point instruction use experiment;
(21) Dual Nios II CPU core experiment;
(22) UCOSII operating system experiment;
(23) Uclinux operating system porting experiment (Note: Provide porting tutorials based on QII5.1. QII7.2 needs to be completed under the Linux operating system. This site only provides reference documents);
(24) Provide tutorials and example projects for porting 8051 single-chip microcomputer core to FPGA. Friends who like 8051 can still have fun on FPGA.
The QII7.2 version of the software has been greatly changed compared with the previous version. Many previous tutorial materials are not very applicable to the 7.2 version. To avoid beginners taking too many detours, our documents are rewritten based on the 7.2 version. And for beginners, several detailed experimental tutorials are written to lead beginners to quickly master the application development of FPGA and SOPC step by step.
FPGA_LED: Use one button to control the on/off of one LED. The simplest experiment allows beginners to familiarize themselves with the use of QII software, master the FPGA development process. The document is illustrated with pictures, describing each step and precautions in detail, allowing beginners to easily get started with FPGA development.
FPGA_74SEG: Design a dynamic 4-bit digital tube display circuit and waveform simulation experiment, allowing beginners to gradually enter FPGA development from shallow to deep, and learn and master circuit simulation using QII.
SOPC_LED: Design the simplest SOPC system, composed of Nios II CPU + on-chip memory + LED, learn the basic process of SOPC development, learn the basic use of SOPC Builder and the writing and online debugging of C programs in the Nios integrated development environment (NiosIDE).
SOPC_LED_BF: Add SDRAM controller and Flash controller to the SOPC system, learn the usage methods of SDRAM and Flash, burn the debugged program into Flash, and the program is automatically downloaded to SDRAM for execution after power-on.
EP1C12 type: 880 yuan/set (purchase model: T1C12-V5)
EP2C5 type: 730 yuan/set (purchase model: T2C5-V5)
EP2C8 type: 860 yuan/set (purchase model: T2C8-V5)
EP3C25 type: 1260 yuan/set (purchase model: T3C25-V5)
Freight: 20 yuan
Purchase method:
http://www.yheda.com/Article/ShowArticle.asp?ArticleID=8409
QQ: 342665334 952183045
Email:
wen_zl@163.com
MSN:
wen_zl@163.com
Consultation phone: 13840376790 024-64664047
Website:
http://www.yheda.com
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OMAP3530 development board, STM32 development board, NXP/LPC development board, S3C44B0 development board, S3C2410 development board, S3C2440 development board, S3C6410 development board, HJTAG emulator, JLINK emulator, MULTI ICE emulator;
FPGA/CPLD products:
EP1C6 development, EP1C12 development board, EP2C5 development board, EP2C8 development board, EP2C20 development board, EP2C35 development board, EP3C25 development board, XC2S50 development board, XC3S400 development board, XC3S700 development board, XC3S1400 development board, EPM7128 development board, EPM1270 development board, USB BLASTER download cable, XILINX USB download cable, ByteBlasterII download cable;
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