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中国DOS联盟论坛 » 网络日志（Blog） » 3龙芯系列电脑硬件和相关信息搜集 <丙申羊年20160206>

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zzz19760225
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『第 106 楼』: 龙芯3A片内集成四个GS464处理器核使用 LLM 解释/回答一下

龙芯3A3000/3B3000 处理器

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多核处理器架构、寄存器描述与系统软件编程指南V1.3

http://www.loongson.cn/uploadfile/cpu/3A3000/Loongson3A3000_3B3000user1.pdf

Last edited by zzz19760225 on 2017-11-21 at 08:00 ]

1<词>，2，3/段\，4{节}，5(章)。

2017-10-2 12:48

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zzz19760225
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『第 107 楼』: 使用 LLM 解释/回答一下

目录

1 概述..........................................................................................................................11
1.1 龙芯系列处理器介绍..................................................................................... 11
1.2 龙芯 3A3000/3B3000 简介............................................................................. 12

2 系统配置与控制......................................................................................................15
2.1 芯片工作模式................................................................................................. 15
2.2 控制引脚说明................................................................................................. 15
2.3 Cache 一致性.................................................................................................. 17
2.4 系统节点级的物理地址空间分布................................................................. 17
2.5 地址路由分布与配置..................................................................................... 19
2.6 芯片配置及采样寄存器................................................................................. 25

3 GS464e 处理器核.....................................................................................................30

4 共享 Cache（SCache）...........................................................................................32

5 矩阵处理加速器......................................................................................................34

6 处理器核间中断与通信..........................................................................................37

7 I/O 中断...................................................................................................................40

8 温度传感器..............................................................................................................43
8.1 实时温度采样................................................................................................. 43
8.2 高低温中断触发............................................................................................. 43
8.3 高温自动降频设置......................................................................................... 44

9 DDR2/3 SDRAM 控制器配置.....................................................................................46
9.1 DDR2/3 SDRAM 控制器功能概述.................................................................... 46
9.2 DDR2/3 SDRAM 读操作协议............................................................................ 46
9.3 DDR2/3 SDRAM 写操作协议............................................................................ 47
9.4 DDR2/3 SDRAM 参数配置格式........................................................................ 47

9.5 软件编程指南................................................................................................. 51
9.5.1 初始化操作............................................................................................ 51
9.5.2 复位引脚的控制.................................................................................... 51
9.5.3 Leveling................................................................................................ 53
9.5.3.1 Write Leveling..............................................................................53
9.5.3.2 Gate Leveling................................................................................54
9.5.4 单独发起 MRS 命令................................................................................ 55
9.5.5 任意操作控制总线................................................................................ 56
9.5.6 自循环测试模式控制............................................................................ 56
9.5.7 ECC 功能使用控制................................................................................. 57

10 HyperTransport 控制器.......................................................................................58
10.1 HyperTransport 硬件设置及初始化.......................................................... 58
10.2 HyperTransport 协议支持.......................................................................... 61
10.3 HyperTransport 中断支持.......................................................................... 62
10.4 HyperTransport 地址窗口.......................................................................... 62
10.4.1 HyperTransport 空间......................................................................... 62
10.4.2 HyperTransport 控制器内部窗口配置............................................. 63

10.5 配置寄存器................................................................................................... 64
10.5.1 Bridge Control.................................................................................. 66
10.5.2 Capability Registers...................................................................... 66
10.5.3 自定义寄存器...................................................................................... 69
10.5.4 接收诊断寄存器.................................................................................. 71
10.5.5 中断路由方式选择寄存器.................................................................. 71
10.5.6 接收缓冲区初始寄存器...................................................................... 71
10.5.7 接收地址窗口配置寄存器.................................................................. 72
10.5.8 中断向量寄存器.................................................................................. 75
10.5.9 中断使能寄存器.................................................................................. 78
10.5.10 Interrupt Discovery & Configuration...................................... 81
10.5.11 POST 地址窗口配置寄存器............................................................... 82
10.5.12 可预取地址窗口配置寄存器............................................................ 83
10.5.13 UNCACHE 地址窗口配置寄存器......................................................... 84
10.5.14 P2P 地址窗口配置寄存器................................................................. 87
10.5.15 命令发送缓存大小寄存器................................................................ 89
10.5.16 数据发送缓存大小寄存器................................................................ 89
10.5.17 发送缓存调试寄存器........................................................................ 89
10.5.18 PHY 阻抗匹配控制寄存器................................................................. 90
10.5.19 Revision ID 寄存器........................................................................ 91
10.5.20 Error Retry 控制寄存器................................................................ 91
10.5.21 Retry Count 寄存器........................................................................ 92
10.5.22 Link Train 寄存器.......................................................................... 92
10.5.23 Training 0 超时短计时寄存器...................................................... 93
10.5.24 Training 0 超时长计时寄存器...................................................... 94
10.5.25 Training 1 计数寄存器.................................................................. 94
10.5.26 Training 2 计数寄存器.................................................................. 94
10.5.27 Training 3 计数寄存器.................................................................. 94
10.5.28 软件频率配置寄存器........................................................................ 95
10.5.29 PHY 配置寄存器................................................................................ 96
10.5.30 链路初始化调试寄存器.................................................................... 97
10.5.31 LDT 调试寄存器................................................................................. 97
10.6 HyperTransport 总线配置空间的访问方法.............................................. 98
10.7 HyperTransport 多处理器支持.................................................................. 98

11 低速 IO 控制器配置............................................................................................101
11.1 PCI 控制器.................................................................................................. 101
11.2 LPC 控制器.................................................................................................. 106
11.3 UART 控制器................................................................................................ 107
11.3.1 数据寄存器（DAT）...........................................................................108
11.3.2 中断使能寄存器（IER）.................................................................... 108
11.3.3 中断标识寄存器（IIR）..................................................................... 108
11.3.4 FIFO 控制寄存器（FCR）.................................................................. 109
11.3.5 线路控制寄存器（LCR）...................................................................109
11.3.6 MODEM 控制寄存器（MCR）...........................................................111
11.3.7 线路状态寄存器（LSR）................................................................... 111
11.3.8 MODEM 状态寄存器（MSR）.........................................................113
11.3.9 分频锁存器...........................................................................................113
11.4 SPI 控制器.................................................................................................. 114
11.4.1 控制寄存器（SPCR）.........................................................................114
11.4.2 状态寄存器（SPSR）......................................................................... 115
11.4.3 数据寄存器（TxFIFO）......................................................................115
11.4.4 外部寄存器（SPER）......................................................................... 115
11.4.5 参数控制寄存器（SFC_PARAM）....................................................116
11.4.6 片选控制寄存器（SFC_SOFTCS）...................................................116
11.4.7 时序控制寄存器（SFC_TIMING）................................................... 117
11.5 IO 控制器配置............................................................................................ 118

12 芯片配置寄存器列表..........................................................................................122

13 软硬件设计指南..................................................................................................162
13.1 硬件改动指南............................................................................................. 162
13.2 频率设置说明............................................................................................. 163
13.3 PMON 改动指南............................................................................................ 163
13.4 内核改动指南............................................................................................. 164

图目录
图 1- 1 龙芯 3 号系统结构..........................................................................................11
图 1- 2 龙芯 3 号节点结构..........................................................................................12
图 1- 3 龙芯 3A3000/3B3000 芯片结构..................................................................... 13
图 3- 1 GS464e 结构图................................................................................................31
图 7- 1 龙芯 3A3000/3B3000 处理器中断路由示意图............................................. 40
图 9- 1 DDR2 SDRAM 读操作协议........................................................................... 47
图 9- 2 DDR2 SDRAM 写操作协议........................................................................... 47
图 10- 1 龙芯 3A3000/3B3000 中 HT 协议的配置访问...........................................98
图 10- 2 四片龙芯 3 号互联结构................................................................................99
图 10- 3 两片龙芯 3 号 8 位互联结构......................................................................100
图 10- 4 两片龙芯 3 号 16 位互联结构....................................................................100
图 11- 1 配置读写总线地址生成.............................................................................105

表目录
表 2- 1 控制引脚说明.................................................................................................15
表 2- 2 节点级的系统全局地址分布.........................................................................17
表 2- 3 节点内的地址分布.........................................................................................18
表 2- 4 节点内的地址分布.........................................................................................18
表 2- 5 MMAP 字段对应的该空间访问属性.............................................................19
表 2- 6 一级交叉开关地址窗口寄存器表.................................................................19
表 2- 7 二级 XBAR 处，从设备号与所述模块的对应关系....................................22
表 2- 8 MMAP 字段对应的该空间访问属性.............................................................22
表 2- 9 二级 XBAR 地址窗口转换寄存器表.............................................................22
表 2- 10 二级 XBAR 缺省地址配置...........................................................................25
表 2- 11 芯片配置寄存器（物理地址 0x1fe00180）...............................................25
表 2- 12 芯片采样寄存器（物理地址 0x1fe00190）...............................................25
表 2- 13 芯片结点和处理器核软件倍频设置寄存器（物理地址 0x1fe001b0）...27
表 2- 14 芯片内存和 HT 时钟软件倍频设置寄存器（物理地址 0x1fe001c0）....28
表 2- 15 芯片处理器核软件分频设置寄存器（物理地址 0x1fe001d0）...............28

表 4- 1 共享 Cache 锁窗口寄存器配置.....................................................................33
表 5- 1 矩阵处理编程接口说明.................................................................................34
表 5- 2 矩阵处理寄存器地址说明.............................................................................35
表 5- 3 trans_ctrl 寄存器说明......................................................................................35
表 5- 4 trans_status 寄存器说明..................................................................................36
表 6- 1 处理器核间中断相关的寄存器及其功能描述..............................................37
表 6- 2 0 号处理器核核间中断与通信寄存器列表...................................................37
表 6- 3 1 号处理器核的核间中断与通信寄存器列表...............................................38
表 6- 4 2 号处理器核的核间中断与通信寄存器列表...............................................38
表 6- 5 3 号处理器核的核间中断与通信寄存器列表...............................................38
表 7- 1 中断控制寄存器..............................................................................................41
表 7- 2 IO 控制寄存器地址.........................................................................................41
表 7- 3 中断路由寄存器的说明..................................................................................42
表 7- 4 中断路由寄存器地址......................................................................................42
表 8- 1 温度采样寄存器说明......................................................................................43
表 8- 2 高低温中断寄存器说明..................................................................................44
表 8- 3 高温降频控制寄存器说明..............................................................................45

表 10- 1 HyperTransport 总线相关引脚信号............................................................. 58
表 10- 2 HyperTransport 接收端可接收的命令......................................................... 61
表 10- 3 两种模式下会向外发送的命令...................................................................61
表 10- 4 默认的 4 个 HyperTransport 接口的地址窗口分布................................... 62
表 10- 5 龙芯 3 号处理器 HyperTransport 接口内部的地址窗口分布................... 63
表 10- 6 龙芯 3A3000/3B3000 处理器 HyperTransport 接口中提供的地址窗口...63
表 10- 7 软件可见寄存器列表...................................................................................64
表 10- 8 Bus Reset Control 寄存器定义..................................................................... 66
表 10- 9 Command，Capabilities Pointer，Capability ID 寄存器定义.....................66
表 10- 10 Link Config，Link Control 寄存器定义.................................................... 67
表 10- 11 Revision ID，Link Freq，Link Error，Link Freq Cap 寄存器定义......... 68
表 10- 12 Feature Capability 寄存器定义................................................................... 69
表 10- 13 MISC 寄存器定义....................................................................................... 69
表 10- 14 接收诊断寄存器..........................................................................................71
表 10- 15 中断路由方式选择寄存器..........................................................................71
表 10- 16 接收缓冲区初始寄存器..............................................................................71

表 10- 17 HT 总线接收地址窗口 0 使能（外部访问）寄存器定义....................... 72
表 10- 18 HT 总线接收地址窗口 0 基址（外部访问）寄存器定义....................... 72
表 10- 19 HT 总线接收地址窗口 1 使能（外部访问）寄存器定义....................... 73
表 10- 20 HT 总线接收地址窗口 1 基址（外部访问）寄存器定义....................... 73
表 10- 21 HT 总线接收地址窗口 2 使能（外部访问）寄存器定义....................... 73
表 10- 22 HT 总线接收地址窗口 2 基址（外部访问）寄存器定义....................... 74
表 10- 23 HT 总线接收地址窗口 3 使能（外部访问）寄存器定义....................... 74
表 10- 24 HT 总线接收地址窗口 3 基址（外部访问）寄存器定义....................... 74
表 10- 25 HT 总线接收地址窗口 4 使能（外部访问）寄存器定义....................... 75
表 10- 26 HT 总线接收地址窗口 4 基址（外部访问）寄存器定义....................... 75

表 10- 27 HT 总线中断向量寄存器定义（1）......................................................... 76
表 10- 28 HT 总线中断向量寄存器定义（2）......................................................... 76
表 10- 29 HT 总线中断向量寄存器定义（3）......................................................... 77
表 10- 30 HT 总线中断向量寄存器定义（4）......................................................... 77
表 10- 31 HT 总线中断向量寄存器定义（6）......................................................... 77
表 10- 32 HT 总线中断向量寄存器定义（7）......................................................... 77
表 10- 33 HT 总线中断向量寄存器定义（8）......................................................... 78
表 10- 34 HT 总线中断使能寄存器定义（1）......................................................... 79
表 10- 35 HT 总线中断使能寄存器定义（2）......................................................... 79
表 10- 36 HT 总线中断使能寄存器定义（3）......................................................... 79
表 10- 37 HT 总线中断使能寄存器定义（4）......................................................... 79
表 10- 38 HT 总线中断使能寄存器定义（5）......................................................... 80
表 10- 39 HT 总线中断使能寄存器定义（6）......................................................... 80
表 10- 40 HT 总线中断使能寄存器定义（7）......................................................... 80
表 10- 41 HT 总线中断使能寄存器定义（8）......................................................... 80

表 10- 42 Interrupt Capability 寄存器定义................................................................. 81
表 10- 43 Dataport 寄存器定义...................................................................................81
表 10- 44 IntrInfo 寄存器定义（1）.......................................................................... 81
表 10- 45 IntrInfo 寄存器定义（2）.......................................................................... 81
表 10- 46 HT 总线 POST 地址窗口 0 使能（内部访问）........................................82
表 10- 47 HT 总线 POST 地址窗口 0 基址（内部访问）........................................82
表 10- 48 HT 总线 POST 地址窗口 1 使能（内部访问）........................................83
表 10- 49 HT 总线 POST 地址窗口 1 基址（内部访问）........................................83
表 10- 50 HT 总线可预取地址窗口 0 使能（内部访问）....................................... 83
表 10- 51 HT 总线可预取地址窗口 0 基址（内部访问）....................................... 84
表 10- 52 HT 总线可预取地址窗口 1 使能（内部访问）....................................... 84
表 10- 53 HT 总线可预取地址窗口 1 基址（内部访问）....................................... 84
表 10- 54 HT 总线 Uncache 地址窗口 0 使能（内部访问）................................... 85
表 10- 55 HT 总线 Uncache 地址窗口 0 基址（内部访问）................................... 85
表 10- 56 HT 总线 Uncache 地址窗口 1 使能（内部访问）................................... 85
表 10- 57 HT 总线 Uncache 地址窗口 1 基址（内部访问）................................... 86
表 10- 58 HT 总线 Uncache 地址窗口 2 使能（内部访问）................................... 86
表 10- 59 HT 总线 Uncache 地址窗口 2 基址（内部访问）................................... 86
表 10- 60 HT 总线 Uncache 地址窗口 3 使能（内部访问）................................... 87
表 10- 61 HT 总线 Uncache 地址窗口 3 基址（内部访问）................................... 87
表 10- 62 HT 总线 P2P 地址窗口 0 使能（外部访问）寄存器定义....................... 87
表 10- 63 HT 总线 P2P 地址窗口 0 基址（外部访问）寄存器定义....................... 88
表 10- 64 HT 总线 P2P 地址窗口 1 使能（外部访问）寄存器定义....................... 88
表 10- 65 HT 总线 P2P 地址窗口 1 基址（外部访问）寄存器定义....................... 88

表 10- 66 命令发送缓存大小寄存器.........................................................................89
表 10- 67 数据发送缓存大小寄存器.........................................................................89
表 10- 68 发送缓存调试寄存器..................................................................................90
表 10- 69 阻抗匹配控制寄存器.................................................................................91
表 10- 70 Revision ID 寄存器..................................................................................... 91
表 10- 71 Error Retry 控制寄存器............................................................................. 91
表 10- 72 Retry Count 寄存器..................................................................................... 92
表 10- 73 Link Train 寄存器........................................................................................92
表 10- 74 Training 0 超时短计时寄存器................................................................... 93
表 10- 75 Training 0 超时长计数寄存器................................................................... 94
表 10- 76 Training 1 计数寄存器............................................................................... 94
表 10- 77 Training 2 计数寄存器............................................................................... 94
表 10- 78 Training 3 计数寄存器............................................................................... 95
表 10- 79 软件频率配置寄存器.................................................................................95
表 10- 80 PHY 配置寄存器........................................................................................96
表 10- 81 链路初始化调试寄存器.............................................................................97
表 10- 82 LDT 调试寄存器......................................................................................... 98
表 11- 1 PCI 控制器配置头.......................................................................................101
表 11- 2 PCI 控制寄存器...........................................................................................102
表 11- 3 PCI/PCIX 总线请求与应答线分配............................................................ 105
表 11- 4 LPC 控制器地址空间分布..........................................................................106
表 11- 5 LPC 配置寄存器含义..................................................................................106
表 11- 6 SPI 控制器地址空间分布........................................................................... 114
表 11- 7 IO 控制寄存器.............................................................................................118
表 11- 8 寄存器详细描述.......................................................................................... 119

Last edited by zzz19760225 on 2017-11-21 at 07:57 ]

Contents
1 Overview ..................................................................................................................11
1.1 Introduction to Loongson Series Processors ......................................................... 11
1.2 Introduction to Loongson 3A3000/3B3000 ......................................................... 12

2 System Configuration and Control ..........................................................................15
2.1 Chip Working Modes ............................................................................................ 15
2.2 Control Pin Descriptions ...................................................................................... 15
2.3 Cache Coherence .................................................................................................. 17
2.4 Physical Address Space Distribution at the System Node Level ......................... 17
2.5 Address Routing Distribution and Configuration ................................................. 19
2.6 Chip Configuration and Sampling Registers ......................................................... 25

3 GS464e Processor Core ............................................................................................30

4 Shared Cache (SCache) ...........................................................................................32

5 Matrix Processing Accelerator .................................................................................34

6 Inter - processor Core Interrupts and Communications ..........................................37

7 I/O Interrupts ............................................................................................................40

8 Temperature Sensor ..................................................................................................43
8.1 Real - time Temperature Sampling ........................................................................ 43
8.2 High and Low Temperature Interrupt Triggering ................................................. 43
8.3 High Temperature Automatic Frequency Reduction Setting ................................ 44

9 DDR2/3 SDRAM Controller Configuration .............................................................46
9.1 Overview of DDR2/3 SDRAM Controller Functions ............................................. 46
9.2 DDR2/3 SDRAM Read Operation Protocol ......................................................... 46
9.3 DDR2/3 SDRAM Write Operation Protocol ......................................................... 47
9.4 DDR2/3 SDRAM Parameter Configuration Format ............................................. 47

9.5 Software Programming Guide ............................................................................. 51
9.5.1 Initialization Operations ............................................................................ 51
9.5.2 Control of Reset Pins ................................................................................ 51
9.5.3 Leveling .................................................................................................... 53
9.5.3.1 Write Leveling ..............................................................................53
9.5.3.2 Gate Leveling ................................................................................54
9.5.4 Initiating MRS Commands Individually .................................................... 55
9.5.5 Arbitrary Operation Control Bus .............................................................. 56
9.5.6 Self - cycling Test Mode Control .............................................................. 56
9.5.7 ECC Function Usage Control ................................................................... 57

10 HyperTransport Controller ....................................................................................58
10.1 HyperTransport Hardware Setup and Initialization ........................................ 58
10.2 HyperTransport Protocol Support ..................................................................... 61
10.3 HyperTransport Interrupt Support .................................................................... 62
10.4 HyperTransport Address Window ..................................................................... 62
10.4.1 HyperTransport Space ......................................................................... 62
10.4.2 HyperTransport Controller Internal Window Configuration ................. 63

10.5 Configuration Registers ...................................................................................... 64
10.5.1 Bridge Control .................................................................................. 66
10.5.2 Capability Registers ...................................................................... 66
10.5.3 Custom Registers .................................................................................. 69
10.5.4 Receive Diagnostic Registers .................................................................. 71
10.5.5 Interrupt Routing Mode Selection Register .......................................... 71
10.5.6 Receive Buffer Initial Register .............................................................. 71
10.5.7 Receive Address Window Configuration Register ................................ 72
10.5.8 Interrupt Vector Register ....................................................................... 75
10.5.9 Interrupt Enable Register ....................................................................... 78
10.5.10 Interrupt Discovery & Configuration .............................................. 81
10.5.11 POST Address Window Configuration Register ................................... 82
10.5.12 Prefetchable Address Window Configuration Register ....................... 83
10.5.13 UNCACHE Address Window Configuration Register ........................... 84
10.5.14 P2P Address Window Configuration Register .................................... 87
10.5.15 Command Send Buffer Size Register ................................................... 89
10.5.16 Data Send Buffer Size Register ........................................................... 89
10.5.17 Send Buffer Debug Register ................................................................ 89
10.5.18 PHY Impedance Matching Control Register ....................................... 90
10.5.19 Revision ID Register ........................................................................ 91
10.5.20 Error Retry Control Register ............................................................ 91
10.5.21 Retry Count Register ........................................................................ 92
10.5.22 Link Train Register .......................................................................... 92
10.5.23 Training 0 Timeout Short Timer Register ........................................ 93
10.5.24 Training 0 Timeout Long Timer Register ........................................ 94
10.5.25 Training 1 Count Register ............................................................... 94
10.5.26 Training 2 Count Register ............................................................... 94
10.5.27 Training 3 Count Register ............................................................... 94
10.5.28 Software Frequency Configuration Register ..................................... 95
10.5.29 PHY Configuration Register ................................................................ 96
10.5.30 Link Initialization Debug Register ...................................................... 97
10.5.31 LDT Debug Register ............................................................................ 97

10.6 Access Method for HyperTransport Bus Configuration Space ...................... 98
10.7 HyperTransport Multi - processor Support ...................................................... 98

11 Low - Speed IO Controller Configuration ..............................................................101
11.1 PCI Controller .................................................................................................... 101
11.2 LPC Controller .................................................................................................... 106
11.3 UART Controller .................................................................................................. 107
11.3.1 Data Register (DAT) .............................................................................108
11.3.2 Interrupt Enable Register (IER) ........................................................... 108
11.3.3 Interrupt Identification Register (IIR) .................................................. 108
11.3.4 FIFO Control Register (FCR) .............................................................. 109
11.3.5 Line Control Register (LCR) ..................................................................109
11.3.6 MODEM Control Register (MCR) .........................................................111
11.3.7 Line Status Register (LSR) ................................................................... 111
11.3.8 MODEM Status Register (MSR) .........................................................113
11.3.9 Divider Latch ...........................................................................................113
11.4 SPI Controller .................................................................................................... 114
11.4.1 Control Register (SPCR) .......................................................................114
11.4.2 Status Register (SPSR) ....................................................................... 115
11.4.3 Data Register (TxFIFO) .......................................................................115
11.4.4 External Register (SPER) ....................................................................... 115
11.4.5 Parameter Control Register (SFC_PARAM) ........................................ 116
11.4.6 Chip Select Control Register (SFC_SOFTCS) ...................................... 116
11.4.7 Timing Control Register (SFC_TIMING) ............................................. 117

11.5 IO Controller Configuration ............................................................................... 118

12 Chip Configuration Register List ..........................................................................122

13 Hardware and Software Design Guide ...................................................................162
13.1 Hardware Modification Guide ........................................................................... 162
13.2 Frequency Setting Instructions .......................................................................... 163
13.3 PMON Modification Guide .................................................................................. 163
13.4 Kernel Modification Guide ................................................................................. 164

List of Figures
Figure 1 - 1 Loongson 3 System Structure ......................................................................11
Figure 1 - 2 Loongson 3 Node Structure .......................................................................12
Figure 1 - 3 Loongson 3A3000/3B3000 Chip Structure ................................................. 13
Figure 3 - 1 GS464e Structure Diagram ..........................................................................31
Figure 7 - 1 Loongson 3A3000/3B3000 Processor Interrupt Routing Schematic Diagram ............................................. 40
Figure 9 - 1 DDR2 SDRAM Read Operation Protocol .................................................... 47
Figure 9 - 2 DDR2 SDRAM Write Operation Protocol .................................................... 47
Figure 10 - 1 Configuration Access of HT Protocol in Loongson 3A3000/3B3000 ...........................................98
Figure 10 - 2 Interconnection Structure of Four Loongson 3 Nodes .............................99
Figure 10 - 3 8 - bit Interconnection Structure of Two Loongson 3 Nodes .........................100
Figure 10 - 4 16 - bit Interconnection Structure of Two Loongson 3 Nodes ......................100
Figure 11 - 1 Configuration Read/Write Bus Address Generation ...................................105

List of Tables
Table 2 - 1 Control Pin Descriptions ...............................................................................15
Table 2 - 2 System Global Address Distribution at the Node Level ...............................17
Table 2 - 3 Address Distribution within the Node ...........................................................18
Table 2 - 4 Address Distribution within the Node ...........................................................18
Table 2 - 5 Access Attributes of the Space Corresponding to the MMAP Field ............19
Table 2 - 6 First - level Crossbar Address Window Register Table ...................................19
Table 2 - 7 Correspondence between Slave Device Number and the Module at the Second - level XBAR ............................22
Table 2 - 8 Access Attributes of the Space Corresponding to the MMAP Field ............22
Table 2 - 9 Second - level XBAR Address Window Conversion Register Table ............22
Table 2 - 10 Default Address Configuration at the Second - level XBAR .......................25
Table 2 - 11 Chip Configuration Register (Physical Address 0x1fe00180) ......................25
Table 2 - 12 Chip Sampling Register (Physical Address 0x1fe00190) ............................25
Table 2 - 13 Chip Node and Processor Core Software Frequency Multiplication Setting Register (Physical Address 0x1fe001b0) ...27
Table 2 - 14 Chip Memory and HT Clock Software Frequency Multiplication Setting Register (Physical Address 0x1fe001c0) ....28
Table 2 - 15 Chip Processor Core Software Divider Setting Register (Physical Address 0x1fe001d0) ................................28

Table 4 - 1 Shared Cache Lock Window Register Configuration .....................................33
Table 5 - 1 Matrix Processing Programming Interface Description ..............................34
Table 5 - 2 Matrix Processing Register Address Description .........................................35
Table 5 - 3 trans_ctrl Register Description ....................................................................35
Table 5 - 4 trans_status Register Description ................................................................36
Table 6 - 1 Registers Related to Inter - processor Core Interrupts and Their Function Descriptions ......................................37
Table 6 - 2 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 0 ..........................37
Table 6 - 3 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 1 ..........................38
Table 6 - 4 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 2 ..........................38
Table 6 - 5 List of Inter - processor Core Interrupts and Communication Registers for Processor Core 3 ..........................38
Table 7 - 1 Interrupt Control Register ............................................................................41
Table 7 - 2 IO Control Register Address .........................................................................41
Table 7 - 3 Description of Interrupt Routing Registers ...................................................42
Table 7 - 4 Interrupt Routing Register Address ...............................................................42
Table 8 - 1 Temperature Sampling Register Description ..................................................43
Table 8 - 2 High and Low Temperature Interrupt Register Description ..........................44
Table 8 - 3 High Temperature Frequency Reduction Control Register Description ......45

Table 10 - 1 HyperTransport Bus - related Pin Signals ................................................... 58
Table 10 - 2 Commands Receivable at the HyperTransport Receive End ...................... 61
Table 10 - 3 Commands Sent Out in Two Modes ............................................................61
Table 10 - 4 Default Address Window Distribution of 4 HyperTransport Interfaces ..... 62
Table 10 - 5 Address Window Distribution within the Loongson 3 Processor HyperTransport Interface .......................... 63
Table 10 - 6 Address Windows Provided in the HyperTransport Interface of Loongson 3A3000/3B3000 Processor ...........63
Table 10 - 7 List of Software - visible Registers .............................................................64
Table 10 - 8 Bus Reset Control Register Definition ......................................................... 66
Table 10 - 9 Command, Capabilities Pointer, Capability ID Register Definition .............66
Table 10 - 10 Link Config, Link Control Register Definition ......................................... 67
Table 10 - 11 Revision ID, Link Freq, Link Error, Link Freq Cap Register Definition ... 68
Table 10 - 12 Feature Capability Register Definition ..................................................... 69
Table 10 - 13 MISC Register Definition ......................................................................... 69
Table 10 - 14 Receive Diagnostic Register .....................................................................71
Table 10 - 15 Interrupt Routing Mode Selection Register .............................................71
Table 10 - 16 Receive Buffer Initial Register ..................................................................71

Table 10 - 17 HT Bus Receive Address Window 0 Enable (External Access) Register Definition ....................................... 72
Table 10 - 18 HT Bus Receive Address Window 0 Base Address (External Access) Register Definition ............................... 72
Table 10 - 19 HT Bus Receive Address Window 1 Enable (External Access) Register Definition ....................................... 73
Table 10 - 20 HT Bus Receive Address Window 1 Base Address (External Access) Register Definition ............................... 73
Table 10 - 21 HT Bus Receive Address Window 2 Enable (External Access) Register Definition ....................................... 73
Table 10 - 22 HT Bus Receive Address Window 2 Base Address (External Access) Register Definition ............................... 74
Table 10 - 23 HT Bus Receive Address Window 3 Enable (External Access) Register Definition ....................................... 74
Table 10 - 24 HT Bus Receive Address Window 3 Base Address (External Access) Register Definition ............................... 74
Table 10 - 25 HT Bus Receive Address Window 4 Enable (External Access) Register Definition ....................................... 75
Table 10 - 26 HT Bus Receive Address Window 4 Base Address (External Access) Register Definition ............................... 75

Table 10 - 27 HT Bus Interrupt Vector Register Definition (1) ........................................ 76
Table 10 - 28 HT Bus Interrupt Vector Register Definition (2) ........................................ 76
Table 10 - 29 HT Bus Interrupt Vector Register Definition (3) ........................................ 77
Table 10 - 30 HT Bus Interrupt Vector Register Definition (4) ........................................ 77
Table 10 - 31 HT Bus Interrupt Vector Register Definition (6) ........................................ 77
Table 10 - 32 HT Bus Interrupt Vector Register Definition (7) ........................................ 77
Table 10 - 33 HT Bus Interrupt Vector Register Definition (8) ........................................ 78
Table 10 - 34 HT Bus Interrupt Enable Register Definition (1) ........................................ 79
Table 10 - 35 HT Bus Interrupt Enable Register Definition (2) ........................................ 79
Table 10 - 36 HT Bus Interrupt Enable Register Definition (3) ........................................ 79
Table 10 - 37 HT Bus Interrupt Enable Register Definition (4) ........................................ 79
Table 10 - 38 HT Bus Interrupt Enable Register Definition (5) ........................................ 80
Table 10 - 39 HT Bus Interrupt Enable Register Definition (6) ........................................ 80
Table 10 - 40 HT Bus Interrupt Enable Register Definition (7) ........................................ 80
Table 10 - 41 HT Bus Interrupt Enable Register Definition (8) ........................................ 80

Table 10 - 42 Interrupt Capability Register Definition ................................................... 81
Table 10 - 43 Dataport Register Definition .....................................................................81
Table 10 - 44 IntrInfo Register Definition (1) ............................................................... 81
Table 10 - 45 IntrInfo Register Definition (2) ............................................................... 81
Table 10 - 46 HT Bus POST Address Window 0 Enable (Internal Access) .......................82
Table 10 - 47 HT Bus POST Address Window 0 Base Address (Internal Access) ...............82
Table 10 - 48 HT Bus POST Address Window 1 Enable (Internal Access) .......................83
Table 10 - 49 HT Bus POST Address Window 1 Base Address (Internal Access) ...............83
Table 10 - 50 HT Bus Prefetchable Address Window 0 Enable (Internal Access) ............ 83
Table 10 - 51 HT Bus Prefetchable Address Window 0 Base Address (Internal Access) ............ 84
Table 10 - 52 HT Bus Prefetchable Address Window 1 Enable (Internal Access) ............ 84
Table 10 - 53 HT Bus Prefetchable Address Window 1 Base Address (Internal Access) ............ 84
Table 10 - 54 HT Bus Uncache Address Window 0 Enable (Internal Access) ................... 85
Table 10 - 55 HT Bus Uncache Address Window 0 Base Address (Internal Access) ........... 85
Table 10 - 56 HT Bus Uncache Address Window 1 Enable (Internal Access) ................... 85
Table 10 - 57 HT Bus Uncache Address Window 1 Base Address (Internal Access) ........... 86
Table 10 - 58 HT Bus Uncache Address Window 2 Enable (Internal Access) ................... 86
Table 10 - 59 HT Bus Uncache Address Window 2 Base Address (Internal Access) ........... 86
Table 10 - 60 HT Bus Uncache Address Window 3 Enable (Internal Access) ................... 87
Table 10 - 61 HT Bus Uncache Address Window 3 Base Address (Internal Access) ........... 87
Table 10 - 62 HT Bus P2P Address Window 0 Enable (External Access) Register Definition ........................................ 87
Table 10 - 63 HT Bus P2P Address Window 0 Base Address (External Access) Register Definition ........................................ 88
Table 10 - 64 HT Bus P2P Address Window 1 Enable (External Access) Register Definition ........................................ 88
Table 10 - 65 HT Bus P2P Address Window 1 Base Address (External Access) Register Definition ........................................ 88

Table 10 - 66 Command Send Buffer Size Register .........................................................89
Table 10 - 67 Data Send Buffer Size Register .................................................................89
Table 10 - 68 Send Buffer Debug Register .......................................................................90
Table 10 - 69 Impedance Matching Control Register .......................................................91
Table 10 - 70 Revision ID Register ................................................................................. 91
Table 10 - 71 Error Retry Control Register ..................................................................... 91
Table 10 - 72 Retry Count Register ................................................................................. 92
Table 10 - 73 Link Train Register ....................................................................................92
Table 10 - 74 Training 0 Timeout Short Timer Register ................................................. 93
Table 10 - 75 Training 0 Timeout Long Timer Register ................................................. 94
Table 10 - 76 Training 1 Count Register ......................................................................... 94
Table 10 - 77 Training 2 Count Register ......................................................................... 94
Table 10 - 78 Training 3 Count Register ......................................................................... 95
Table 10 - 79 Software Frequency Configuration Register .............................................95
Table 10 - 80 PHY Configuration Register ......................................................................96
Table 10 - 81 Link Initialization Debug Register .............................................................97
Table 10 - 82 LDT Debug Register ................................................................................... 98
Table 11 - 1 PCI Controller Configuration Header .........................................................101
Table 11 - 2 PCI Control Register ...................................................................................102
Table 11 - 3 PCI/PCIX Bus Request and Acknowledge Line Allocation ........................ 105
Table 11 - 4 LPC Controller Address Space Distribution ................................................106
Table 11 - 5 LPC Configuration Register Meaning .......................................................106
Table 11 - 6 SPI Controller Address Space Distribution ................................................. 114
Table 11 - 7 IO Control Register .....................................................................................118
Table 11 - 8 Register Detailed Description .................................................................... 119

Last edited by zzz19760225 on 2017-11-21 at 07:57 ]

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概述，介绍分类，列图，列表。

3 GS464e 处理器核.....................................................................................................30

12 芯片配置寄存器列表..........................................................................................122

13 软硬件设计指南..................................................................................................162
13.1 硬件改动指南............................................................................................. 162

Last edited by zzz19760225 on 2017-11-21 at 08:01 ]

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龙芯 1A 具有以下关键特性：
• 集成一个 LS232 双发射龙芯处理器核，指令和数据 L1 Cache 各 16KB
• 集成 2D GPU
• 集成两路 DC 控制器，最大分辨率可支持到 1920*1080@60Hz/24bit
• 集成 2 个 10M/100M/1000M 自适应 GMAC
• 集成 2 个 SATA2
• 集成 32 位 PCI，支持主从模式
• 集成 1 个 32 位/16 位 DDR2 控制器
• 集成 4 个 USB HOST 接口，兼容 USB2.0 和 USB1.1
• 集成 1 个 8 位 NAND FLASH 控制器,支持 4 个片选
• 集成中断控制器，支持灵活的中断设置
• 集成 2 个 SPI 控制器，支持主模式，SPI0 支持系统启动
• 集成 AC97 控制器
• 集成 1 个 LPC 控制器
• 集成 4 路 UART 串口
• 集成 1 路 PS/2(键盘和鼠标)
• 集成 3 路 I2C 控制器，兼容 SMBUS
• 集成 2 路 CAN 总线控制器
• 集成 88 路 GPIO 端口
• 集成 1 路 RTC 接口
• 集成 4 路 PWM 控制器
• 集成 ACPI
• 集成看门狗

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zhengruohuang：
toddler C 语言操作系统
https://github.com/zhengruohuang/toddler

如何从零开始写一个简单的操作系统？
https://www.zhihu.com/question/25628124

Last edited by zzz19760225 on 2017-12-7 at 15:21 ]

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loongson2f_龙芯灵珑9S2A一体机尝试usb和硬盘两种方式安装debian6成功篇：linkasm
http://blog.csdn.net/v80/article/details/78595967

Last edited by zzz19760225 on 2017-11-23 at 15:30 ]

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